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| ADVANCED COMMUNCIATIONS Description The ACS8515 is a highly integrated, single-chip solution for hit-less protection switching of SEC clocks from Master and Slave SETS clockcards in a SONET or SDH Network Element. The ACS8515 has fast activity monitors on the inputs and will implement automatic system protection switching against master clock failure. A further input is provided for an optional standby SEC clock. The ACS8515 is fully compliant with the required specifications and standards. The ACS8515 can perform frequency translation from a SEC input clock distributed along a back plane to a different local line card clock, e.g. 8 kHz distributed on the back plane and 19.44 MHz generated on the line cards. An SPI serial port is incorporated, providing access to the configuration and status registers for device setup. The ACS8515 can utilise either a low cost XO oscillator module, or a TCXO with full temperature calibration - as required by the application. Block Diagram Line Card Protection Switch for SONET or SDH Network Elements FINAL Features Suitable for Stratum 3, 4E and 4 SONET or SDH Equipment Clock (SEC) applications Meets AT&T, ITU-T, ETSI and Telcordia specifications Three SEC input clocks, from 2 kHz to 155.52 MHz Generates two SEC output clocks, up to 311.04 MHz Frequency translation of SEC input clock to a different local line card clock Robust input clock source frequency and activity monitoring on all inputs Supports Free-Run, Locked and Holdover modes of operation Automatic hit-less source switchover on loss of input External force fast switch between SEC inputs Phase build-out for output clock phase continuity during input switchover SPI compatible serial microprocessor interface Programmable wander and jitter tracking/ attenuation 0.1 Hz to 20 Hz Single 3.3 v operation. 5 v I/O compatible Operating temperature (ambient) -40C to +85C Available in 64 pin LQFP package ACS8515 LC/P 3 x SEC Input Master/Slave + Standby: N x 8kHz 1.544MHz 2.048MHz 6.48M Hz 19.44MHz 38.88MHz 51.84MHz 77.76MHz 155.52MHz Plus: MFrSync 3xSEC Input Ports MFrSync APLL DPLL Frequency Synthesis 2xSEC Output Ports FrSync MFrSync Monitors Frequency Dividers 2 x SEC Output including: 1.544/2.048MHz 3.088/4.096MHz 6.176/8.192MHz 12.352/16.384MHz 19.44MHz 38.88MHz 155.52MHz 311.04MHz Plus: 2kHz MFrSync 8kHz FrSync Chip C lock Generator Priority Table Register Set SPI Compatible Serial M icroprocessor Port TCXO or XO Revision 2.05/Jan 2001 a2001 Semtech Corp www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS Table of Contents Pin diagram................................................................................................................................................3 Pin descriptions.........................................................................................................................................4 Functional description...............................................................................................................................6 Local oscillator clock..........................................................................................................................................................6 Input Interfaces..................................................................................................................................................................7 Input reference clock ports................................................................................................................................................7 Input wander and jitter tolerance......................................................................................................................................9 Output clock ports...........................................................................................................................................................10 Output wander and jitter..................................................................................................................................................11 Phase variation.................................................................................................................................................................13 Phase build-out.................................................................................................................................................................15 Microprocessor interface................................................................................................................................................15 Interrupt enable and clear...............................................................................................................................................16 Register map.....................................................................................................................................................................17 Register map description.................................................................................................................................................20 Selection of input reference clock sources...................................................................................................................27 Activity monitoring...........................................................................................................................................................28 Modes of operation..........................................................................................................................................................30 Power on reset - PORB.....................................................................................................................................................31 FINAL Electrical specification............................................................................................................................33 Absolute maximum range...............................................................................................................................................33 Operating conditions.......................................................................................................................................................33 TTL DC characterisitics...................................................................................................................................................33 PECL DC characteristics..................................................................................................................................................35 LVDS DC characteristics..................................................................................................................................................36 Jitter characteristics........................................................................................................................................................37 Microprocessor inter face timing characteristics.......................................................................................41 Serial mode.......................................................................................................................................................................41 Package information................................................................................................................................43 Application information............................................................................................................................45 Simplified application schematic...................................................................................................................................45 Revision History.......................................................................................................................................46 Order information....................................................................................................................................47 Revision 2.05/Jan 2001 a2001 Semtech Corp 2 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS Pin Diagram FINAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AGND IC AGND VA1+ INTREQ REFCLK DGND VD+ VD+ DGND DGND VD+ SRCSW VA2+ AGND IC FrSync MFrSync O1POS O1NEG GND_DIFF VDD_DIFF SEC1_POS SEC1_NEG SEC2_POS SEC2_NEG VDD5 Sync2k SEC1 SEC2 DGND VDD 1 ACS8515 LC/P Rev 2.0 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SONSDHB IC IC IC IC NC DGND VDD O2 NC VDD DGND SDO IC IC IC PORB SCLK VDD VDD CSB SDI CLKE IC DGND VDD VDD IC VDD IC SEC3 IC Top view of 64 pin LQFP package. NC - Not Connected, IC - Internally Connected Revision 2.05/Jan 2001 a2001 Semtech Corp 3 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS Pin Descriptions FINAL Power PIN 8, 9, 12 22 SYM B OL V D+ V DD_DIFF IO P P T YPE - N A M E /DE SCR I P T I O N S u p p l y v o l t ag e : Digital sup p ly to gates in analog section, +3.3 Volts. +/- 10% S u p p l y v o l t ag e : Digital sup p ly for d ifferential outp ut p ins 19 & 20, +3.3 Volts. +/- 10% V D D 5: Digital sup p ly for +5 Volts tolerance to inp ut p ins. Connect to +5 volts (+/- 10%) for clamp ing to +5 v. Connect to V DD for clamp ing to +3.3 v. Leave floating for no clamp ing, inp ut p ins tolerant up to +5.5 v. S u p p l y v o l t ag e : Digital sup p ly to logic, +3.3 Volts. +/- 10% S u p p l y v o l t ag e : A nalog sup p ly to clock multip ying A PLL, +3.3 Volts. +/- 10% S u p p l y v o l t ag e : A nalog sup p ly to outp ut A PLL, +3.3 Volts. +/- 10% S u p p l y G r o u n d : Digital ground for logic S u p p l y G r o u n d : Digital ground for d ifferential outp ut p ins 19 & 20 S u p p l y G r o u n d : A nalog ground 27 V DD5 P - 32, 36, 38, 39, 45, 46, 54, 57 4 14 7, 10, 11, 31, 40, 53, 58 21 1, 3, 15 V DD P - VA 1+ VA 2+ DGN D P P P - GN D_DIFF A GN D P P - No connections PIN 55, 59 2, 16, 60, 61, 62, 63 37 41 49 50 51 SYM B OL NC IC IC IC IC IC IC IO - T YPE - N A M E /DE SCR I P T I O N N ot C on n ect ed : Leave to Float I n t er n al l y C on n ect ed : Leave to Float I n t er n al l y con n ect ed : Leave to Float. Reserved for JTAG control reset inp ut on next revision I n t er n al l y con n ect ed : Leave to Float. Reserved for JTAG test mode select inp ut on next revision I n t er n al l y con n ect ed : Leave to Float. Reserved for JTAG b oundary scan clock inp ut on next revision I n t er n al l y con n ect ed : Leave to Float. Reserved for JTAG serial test data outp ut on next revision I n t er n al l y con n ect ed : Leave to Float. Reserved for JTAG serial test data inp ut on next revision 4 www.semtech.com Revision 2.05/Jan 2001 a2001 Semtech Corp ACS8515 LC/P ADVANCED COMMUNCIATIONS Others PIN 5 6 13 17 18 19 20 23 24 25 26 28 29 30 33 34 35 42 43 44 FINAL N A M E /DE SCR I P T I O N I n t e r u p t r e q u e st : Softw are Interrup t enab le R e f e r e n ce cl o ck : 12.8 MHz (refer to section h ead ed Local Oscillator Clock) S o u r ce sw i t ch i n g : Force fast source sw itch ing on SEC1 and SEC2 O u t p u t r e f e r e n ce : 8 kHz Frame Sync, 50:50 mark/sp ace ratio outp ut O u t p u t r e f e r e n ce : 2 kHz Multi-Frame Sync, 50:50 mark/sp ace ratio outp ut O u t p u t r e f e r e n ce : Programmab le, d efault 38.88 MHz LV DS I n p u t r e f e r e n ce : Programmab le, d efault 19.44 MHz LV DS I n p u t r e f e r e n ce : Programmab le, d efault 19.44 MHz PECL M u l t i - Fr am e S y n c 2 k H z : Multi-Frame Sync inp ut I n p u t r e f e r e n ce : Programmab le, d efault 8 kHz I n p u t r e f e r e n ce : Programmab le, d efault 8 kHz I n t e r n al l y co n n e ct e d : Connect to GN D. Reserved for Slave Multiframe sync 2 kHz inp ut on next revision. I n p u t r e f e r e n ce : External stand b y reference clock source, p rogrammab le, d efault 19.44 MHz I n t e r n al l y co n n e ct e d : Connect to GN D. Reserved for external stand b y 2 kHz Multi-frame sync inp ut on next revision. S C L K e d g e se l e ct : SCLK active ed ge select, CLKE=1 selects falling ed ge of SCLK to b e active M i cr o p r o ce sso r i n t e r f ace ad d r e ss: Serial d ata inp ut C h i p se l e ct ( act i v e l o w ) : Th is p in is asser ted Low b y th e microp rocessor to enab le th e microp rocessor inter face A d d r e ss L at ch E n ab l e : d efault Serial d ata clock. Wh en th is p in transitions from h igh to low, th e ad d ress b us inp uts are latch ed into th e internal registers P o w e r o n r e se t : Master reset. If PORB is forced Low, all internal states are reset b ack to d efault values SYM B OL IN T R E Q REFCLK SRCSW FrSync MFrSync O1POS O1N EG SEC1_POS SEC1_N EG SEC2_POS SEC2_N EG Sync2k SEC1 SEC2 IC SEC3 IC CLKE SDI CSB IO O I I O O O I I I I I I I I I T YPE TTL T T LD TTL TTL LV DS/ PECL LV DS/ PECL PECL/ LV DS T T LD T T LD T T LD T T LD T T LD T T LD T T LU 47 SCLK I T T LD 48 PORB I T T LU Note: I = input, O = output, P = power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor Revision 2.05/Jan 2001 a2001 Semtech Corp 5 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS PIN 52 56 FINAL N A M E /DE SCR I P T I O N M i cr o p r o ce sso r i n t e r f ace ad d r e ss: Serial d ata outp ut O u t p u t r e f e r e n ce : 19.44 MHz fixed S O N E T S D H B : SON ET or SDH freq uency select: sets th e initial p ow er up state (or state after a PORB) of th e SON ET/SDH freq uency selection registers, ad d r 34h , b it 2 and ad d r 38, b it 5. Wh en low SDH rates are selected (2.048 MHz etc) and w h en set h igh SON ET rates are selected (1.544 MHz etc). Th e register states can b e ch anged after p ow er up b y softw are SYM B OL SDO O2 IO O O T YPE T T LD TTL 64 SON SDHB I T T LD Functional description The ACS8515 is a highly integrated, single-chip solution for hit-less protection switching of SEC clocks from Master and Slave SETS clock cards in a SONET or SDH Network Element. The ACS8515 has fast activity monitors on the inputs and will implement automatic system protection switching for Master/Slave SEC clock failure. The standby SEC clock will be selected if both the Master and Slave input clocks fail. The selection of the Master/Slave input can also be forced by a Force Fast Switch pin. The ACS8515 can perform frequency translation from a SEC input clock distributed along a back plane to a different local line card - e.g. 8 kHz distributed on the back plane and 19.44 MHz generated on the line cards. The ACS8515 has three SEC clock inputs (Master, Slave and Standby) and a single MultiFrame Sync input, for synchronising the frame and multi-frame sync outputs. The ACS8515 generates two SEC clock outputs via PECL/LVDS and TTL ports, with spot frequencies from 1.544/2.048 MHz up to 311.04 MHz. The ACS8515 also provides an 8 kHz Frame Sync and 2 kHz Multi-Frame Sync output clock. The ACS8515 has a high tolerance to input jitter and wander. The output jitter and wander are low, where the wander transfer is Revision 2.05/Jan 2001 a2001 Semtech Corp 6 programmable (0.1 Hz up to 20 Hz cut-off points). The ACS8515 includes an SPI compatible serial microprocessor port, providing access to the configuration and status registers for device setup. Local Oscillator Clock The Master system clock on the ACS8515 should be provided by an external clock oscillator of frequency 12.80 MHz. The exact clock specification is dependent on the quality of Holdover performance required in the application. In most Line Card protection switching applications where there is a high chance that at least one SEC reference input will be available, the long term stability requirement for Holdover is not appropriate and an inexpensive crystal local oscillator can be used. In other applications where there may be a requirement for longer term Holdover stability to meet the ITU standards for Stratum 3, a higher quality oscillator can be used. Please contact Semtech for information on crystal oscillator suppliers. Crystal Frequency Calibration The absolute crystal frequency accuracy is less www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS important than the stability since any frequency offset can be compensated by adjustment of register values in the IC. This allows for calibration and compensation of any crystal frequency variation away from its nominal value. +/- 50 ppm adjustment would be sufficient to cope with most crystals, in fact the range is an order of magnitude larger due to the use of two 8 bit register locations. The setting of the conf_nominal_frequency register allows for this adjustment. An increase in the register value increases the output frequencies by 0.02 ppm for each LSB step. The default value (in decimal) is 39321. The minimum being 0 and the maximum 65535, gives a +500 ppm to -700 ppm adjustment range of the output frequencies. For example, if the crystal was oscillating at 12.8 MHz + 5ppm, then the calibration value in the register to give a -5 ppm adjustment in output frequencies to compensate for the crystal inaccuracy, would be : 39321 - (5 / 0.02) = 39071 (decimal). Input Interfaces The ACS8515 supports up to three individual input reference clock sources via TTL/CMOS and PECL/LVDS technologies. These interface technologies support 3.3 V and 5 V operation. Input Reference Clock Ports The input reference clock ports are arranged in groups. Group one comprises a TTL port (SEC1) and a PECL/LVDS port (SEC1POS and SEC1NEG). Group two comprises a TTL port (SEC2) and a PECL/LVDS port (SEC2POS and SEC2NEG). Group three comprises a TTL port (SEC3). For group one and group two, only one of the two input ports types must be active at any time, the other must not be driven by a reference input. Unused PECL/LVDS differential inputs should be fixed with one input high (VDD) and the other low (GND), or set in LVDS mode Revision 2.05/Jan 2001 a2001 Semtech Corp 7 FINAL and left floating (in which case one input is internally pulled high and the other low). SDH and SONET networks use different default frequencies; the network type is selectable using the config_mode register 34 Hex, bit 2. For SONET, config_mode register 34 Hex, bit 2 = 1, for SDH config_mode register 34 Hex, bit 2 = 0. On power-up or by reset, the default will be set by the state of the SONSDHB pin (pin 64). Specific frequencies and priorities are set by configuration. The TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being 77.76 MHz. Clock speeds above 100 MHz should not be applied to the TTL ports. The PECL/LVDS ports support the full range of clock speeds, up to 155.52 MHz. The actual spot frequencies supported are; 8 kHz (and N x 8 kHz), 1.544 MHz/2.048 MHz, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz, and 155.52 MHz. The frequency selection is programmed via the cnfg_ref_source_frequency register. The internal DPLL will normally lock to the selected input at the frequency of the input, eg. 19.44 MHz will lock the DPLL phase comparisons at 19.44 MHz. It is, however, possible to utilise an internal pre-divider to the DPLL to divide the input frequency before it is used for phase comparisons in the DPLL. This pre-divider can be used in one of 2 ways; (i) any of the supported spot frequencies can be divided to 8 kHz by setting the "lock8K" bit (bit 6) in the appropriate cnfg_ref_source_frequency register location (ii) any multiple of any supported frequency can be supported by using the "DivN" feature (bit 7 of the cnfg_ref_source_frequency register). Any reference input can be set to lock at 8 kHz independently of the frequencies and configurations of the other inputs. Any reference input with the "DivN" bit set in the cnfg_ref_source_frequency register will employ the internal pre-divider prior to the DPLL www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS P o r t N am e I n p u t P or t Te c h n o l o g y Fr eq u en ci es S u p p or t ed Up to 100MHz (N ote 1) Default (SON ET): Default (SDH): Up to 100MHz (N ote 1) Default (SON ET): Default (SDH): FINAL S E C S o u r ce G r o u p D e f au l t P ri ori t y (N ote 3) 1 (4) SEC1 TTL/CMOS 8kHz 8kHz 8kHz 8kHz 1 SEC2 TTL/CMOS 2 3 (5) SEC1 LVDS/PECL LVDS default PECL/LVDS PECL default Up to 155.52MHz (N ote 2) Default (SON ET): 19.44MHz Default (SDH): 19.44MHz Up to 155.52MHz (N ote 2) Default (SON ET): 19.44MHz Default (SDH): 19.44MHz Up to 100MHz (N ote 1) Default (SON ET): Default (SDH): 2kHz Multi Frame Sync 19.44MHz 19.44MHz 1 2 (6) SEC2 2 4 (7) SEC3 TTL/CMOS 3 5 (10) SYN C1 TTL/CMOS - - Table 1: Input Reference Source Selection and Group allocation Notes for Table 1. Note 1. TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being 77.76 MHz. The actual spot frequencies are 8 kHz (N x 8 kHz), 1.544/2.048 MHz, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz and 77.76 MHz. Note 2. PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz. There are different output clock frequencies available for SONET and SDH applications. F1/F2 means that the output frequency is F1 for SONET mode selection and F 2 for SDH mode selection. Note 3. The default priority values in brackets are the default numbers reported in the register map, which match up with the ACS8510. On power up, or by reset, the default will be set by the SONSDHB pin. Specific frequencies and priorities are set by configuration. For SONET, config_mode register 34 Hex, bit 2 = 1. For SDH config_mode register 34 Hex, bit 2 = 0. locking. The cnfg_freq_divn register contains the divider ratio N where the reference input will get divided by (N+1) where 0 input set to DivN must have the frequency monitors disabled (if the frequency monitors are disabled, they are disabled for all inputs regardless of the input configurations, in this case only activity monitoring will take place). Whilst any number of inputs can be set to use the DivN feature, only one N can be programmed, hence all inputs using the DivN feature must require the same division to get to 8 kHz. www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz. The choice of PECL or LVDS compatibility is programmed via the cnfg_differential_inputs register. Unused PECL/LVDS differential inputs should be fixed with one input high (VDD) and the other input low (GND), or set in LVDS mode and left floating, in which case one input is internally pulled high and the other low. Input Wander and Jitter Tolerance The ACS8515 is compliant to the requirements of all relevant standards, principally ITU Recommendation G.825, ANSI T1.101-1994 and ETS 300 462-5 (1997). All reference clock inputs have a tight frequency tolerance but a generous jitter tolerance. Pullin, hold-in and pull-out ranges are specified for each input port in Table 2. Minimum jitter tolerance masks are specified in Figures 1 and 2, and Tables 3 and 4, respectively. The ACS8515 will tolerate wander and jitter J i t t er To l e r a n c e G.703 G.783 G.823 GR-1244-CORE +/- 16.6 p p m Fr eq u en cy M on i t or A c c e p t an c e R an g e FINAL components greater than those shown in Figure 1 and Figure 2, up to a limit determined by a combination of the apparent long-term frequency offset caused by wander and the eye-closure caused by jitter (the input source will be rejected if the offset pushes the frequency outside the hold-in range for long enough to be detected, whilst the signal will also be rejected if the eye closes sufficiently to affect the signal purity). The 8klocking mode should be engaged for high jitter tolerance according to these masks. All reference clock ports are monitored for quality, including frequency offset and general activity. Single short-term interruptions in selected reference clocks may not cause rearrangements, whilst longer interruptions, or multiple, short-term interruptions, will cause rearrangements, as will frequency offsets which are sufficiently large or sufficiently long to cause loss-of-lock in the phase-locked loop. The failed reference source will be removed from the priority table and declared as unserviceable, until its perceived quality has been restored to Fr eq u en cy A c c e p t an c e R an g e ( H o l d - i n ) +/- 4.6 p p m (see N ote 1) +/- 9.2 p p m (see N ote 2) Fr eq u en cy A c c e p t an c e R an g e ( P u l l - ou t ) +/- 4.6 p p m (see N ote 1) +/- 9.2 p p m (see N ote 2) Fr eq u en cy A c c e p t an c e R an g e ( Pull-in) +/- 4.6 p p m (see N ote 1) +/- 9.2 p p m (see N ote 2) Table 2: Input Reference Source Jitter Tolerance. Notes for Table 2. Note 1. The frequency acceptance and generation range will be +/-4.6 ppm around the required frequency when the external crystal frequency accuracy is within a tolerance of +/- 4.6 ppm. Note 2. The fundamental acceptance range and generation range is +/- 9.2 ppm with an exact external crystal frequency of 12.8 MHz. Note 3. The power up default PDLL range is as stated in note 2, but the range is also programmable from 0 to 80 ppm in 0.08 ppm steps. Revision 2.05/Jan 2001 a2001 Semtech Corp 9 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS an acceptable level. The registers reg sts_curr_inc_offset (address 0C, 0D, 07) report the frequency of the DPLL with respect to the external TCXO frequency. This is a 19 bit signed number with one LSB representing 0.0003 ppm (range of +/- 80 ppm). Reading this regularly can show how the currently locked source is varying in value e.g. due to wander on its input. The ACS8515 performs automatic frequency monitoring with an acceptable input frequency offset range of +/- 16.6 ppm. The ACS8515 DPLL has a programmable frequency limit of +/- 80 ppm. If the range is programmed to be > 16.6 ppm, the activity monitors should be FINAL disabled so the input reference source is not automatically rejected as out of frequency range. Output Clock Ports The ACS8515 supports two SEC output clocks on both TTL and PECL/LVDS ports and a pair of secondary output clocks, Frame-Sync and Multi-Frame-Sync. The two output clocks are individually controllable. The Frame-Sync and Multi-Frame-Sync are derived from the main SEC clock. The frequencies of the output clock are selectable from a range of pre-defined spot frequencies, and a variety of output technologies are supported, as defined in Table 5. $ $ $ $ $ I I I I I -LWWHU DQG ZDQGHU IUHTXHQF\ ORJ VFDOH I I I I Figure 1: Minimum Input Jitter Tolerance for inputs supporting G.783 compliant sources P e ak t o p e ak am p l i t u d e ( u n i t I n t e r v al ) A0 2800 A1 311 A2 39 A3 1.5 A4 0.15 F0 12u F1 178u F2 1.6m F3 15.6m ST M l evel Fr eq u en cy ( H z ) F4 0.125 F5 19.3 F6 500 F7 6.5k F8 65k F9 1.3m STM-1 Table 3: Amplitude and Frequency values for Jitter Tolerance for inputs supporting G.783 compliant sources Revision 2.05/Jan 2001 a2001 Semtech Corp 10 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS 3HDNWRSHDN MLWWHU DQG ZDQGHU DPSOLWXGH ORJ VFDOH $ FINAL $ -LWWHU DQG ZDQGHU IUHTXHQF\ ORJ VFDOH I I I I Figure 2: Minimum Input Jitter Tolerance for inputs supporting G.703 compliant sources Ty p e S p ec. A mp litud e ( U I p k-p k) A1 DS1 E1 G R - 1244- C O R E I T U G. 823 5 1.5 A2 0.1 0.2 F1 10 20 Fr e q u e n cy ( Hz ) F2 500 2.4k F3 8k 18k F4 40k 100k Table 4: Amplitude and Frequency values for Jitter Tolerance for inputs supporting G.703 compliant sources Low-speed Output Clock Frame Sync and Multi-Frame Sync Clocks The O2 SEC clock is supplied on a TTL port with a fixed frequency of 19.44 MHz. High-speed Output Clock Frame Sync (8 kHz) and Multi-Frame Sync (2 kHz) clocks will be provided on outputs FrSync and MFrSync. The FrSync and MFrSync clocks have a 50:50 mark space ratio. Output Wander and Jitter Wander and jitter present on the output clocks are dependent on: The magnitude of wander and jitter on the selected input reference clock (in locked mode); The internal wander and jitter transfer characteristic (in locked mode); The jitter on the local oscillator clock; The wander on the local oscillator clock (in Hold-Over mode). www.semtech.com The O1 SEC clock is supplied on a PECL/LVDS port with spot frequencies of 19.44 MHz, 38.88 MHz, 155.52 MHz, 311.04 MHz and Dig 1 (where Dig 1 is 1.544/2.048 MHz and multiples of 2, 4 and 8 depending on SONET/SDH mode setting). The actual frequency is selectable via the cnfg_differential_outputs register. The O1 port can also support 311.04 MHz, which is enabled via the cnfg_T0_output_enable register. The O1 port can be made LVDS or PECL compatible via the cnfg_differential_outputs register. Revision 2.05/Jan 2001 a2001 Semtech Corp 11 ACS8515 LC/P ADVANCED COMMUNCIATIONS Wander and jitter are treated in different ways to reflect their differing impacts on network design. Jitter is always strongly attenuated, whilst wander attenuation can be varied to suit the application and operating state. Wander and jitter attenuation is performed by using a digital phase locked loop (DPLL) with a programmable bandwidth. This gives a transfer characteristic of a low pass filter, with a programmable pole. It is sometimes necessary to change the filter dynamics to suit particular circumstances - one example being when locking to a new source, the filter can be opened up to reduce locking time and can then be gradually tightened again to remove wander. Since wander represents a relatively long-term deviation from the nominal operating frequency, it affects the rate of supply of data to the network element. Strong wander attenuation limits the rate of consumption of data to within a smaller range, so a larger buffer store is required to prevent data loss. But, since any buffer store potentially increases latency, wander may often only need to be removed at P or t N am e O1 O2 FrSync MFrSync FINAL specific points within a network where buffer stores are acceptable, such as at digital cross connects. Otherwise, wander is sometimes not required to be attenuated and can be passed through transparently. The ACS8515 has programmable wander transfer characteristics in a range from 0.1 Hz to 20 Hz. The wander and jitter transfer characteristic is shown in Figure 3. Wander on the local oscillator clock will not have significant effect on the output clock whilst in locked mode, so long as the DPLL bandwidth is set high enough so that the DPLL can compensate quickly enough for any frequency changes in the crystal. In free-running or Holdover mode wander on the crystal is more significant. Variation in crystal temperature or supply voltage both cause drifts in operating frequency, as does ageing. These effects must be limited by careful selection of a suitable component for the local oscillator, as specified in the section Local Oscillator Clock. O u t p u t P or t Te c h n o l o g y LVDS/PECL LVDS default TTL/CMOS TTL/CMOS TTL/CMOS Fr eq u en ci es S u p p or t ed (N ote 1) 19.44 MHz, 38.88 MHz (default), 155.52 MHz, 311.04 MHz, Dig1 Dig1 is 1.544 MHz/2.048 MHz and multip les of 2, 4 and 8 19.44MHz fixed FrSync, 8kHz. 50:50 mark/sp ace ratio MFrSync, 2kHz. 50:50 mark/sp ace ratio Table 5: Output Reference Source Selection table Notes for Table 5. Note 1. There are different output clock frequencies available for SONET and SDH applications. Dig 1 can be configured for either frequency F1/F2, where the output frequency is F1 when the SONET mode is selected, and F2 when the SDH mode is selected. On power up, or by reset, the default will be set by the SONSDHB pin. Specific frequencies and priorities are set by configuration. For SONET, config_mode register 34 Hex, bit 2 = 1. For SDH config_mode register 34 Hex, bit 2 = 0. Revision 2.05/Jan 2001 a2001 Semtech Corp 12 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS 3HDNWRSHDN MLWWHU DQG ZDQGHU DPSOLWXGH ORJ VFDOH -LWWHU FXWRII ORZ IUHTXHQF\ -LWWHU FXWRII KLJK IUHTXHQF\ +] +] FINAL 8, # I G% G% -LWWHU DQG ZDQGHU IUHTXHQF\ ORJ VFDOH Figure 3: Wander and Jitter Transfer Characteristsics Phase Variation There will be a phase shift across the ACS8515 between the selected input reference source and the output clock. This phase shift may vary over time but will be constrained to lie within specified limits. The phase shift is characterised using two parameters, MTIE (Maximum Time Interval Error), and TDEV (Time Deviation), which, although being specified in all relevent specifications, differ in acceptable limits in each one. Typical measurements for the ACS8515 are shown in Figures 4 and 5, for locked mode operation. Figure 6 shows a typical measurement of Phase Error accumulation in Holdover mode operation. The required performance for phase variation during Holdover is specified in several ways depending upon the particular circumstances pertaining: 1. ETSI 300 462-5, Section 9.1, requires that the shortterm phase error during switchover (i.e., Locked to Holdover to Locked) be limited to an accumulation rate no greater than 0.05 ppm during a 15 second interval. Revision 2.05/Jan 2001 a2001 Semtech Corp 13 2. ETSI 300 462-5, Section 9.2, requires that the longterm phase error in the Holdover mode should not exceed {(a1+a2)S+0.5bS2+c}, where a1 = 50 ns/s (allowance for initial frequency offset) a2 = 2000 ns/s (allowance for temperature variation) b = 1.16x10-4 ns/s2 (allowance for ageing) c = 120 ns (allowance for entry into Holdover mode). 3. ANSI Tin1.101-1994, Section 8.2.2, requires that the phase variation be limited so that no more than 255 slips (of 125 s each) occur during the first day of Holdover. This requires a frequency accuracy better than: ((24x60x60)+(255x125s))/(24x60x60) = 0.37 ppm. Temperature variation is not restricted, except to within the normal bounds of 0 to 50 Celsius. 4. Bellcore GR.1244.CORE, Section 5.2. Table 4. shows that an initial frequency offset of 50 ppb is permitted on entering Holdover, whilst a drift over temperature of 280 ppb is allowed; an allowance of 40 ppb is permitted for all other effects. 5. ITU G.822, Section 2.6, requires that the slip rate www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS FINAL 1 00 T im e (n s) 10 G .8 1 3 o p tion 1 , co n sta n t te m p e rature w an de r lim it 1 M T IE m e a su re m e n t o n 1 5 5 M H z o u tp u t, 1 9.44 M H z i/p (8 kH z lo ckin g), V e c tro n 6 6 6 4 x tal 0 .1 0 .0 1 0 .01 0.1 1 10 100 1000 10000 O b s erv a tio n in terva l (s) Figure 4: Maximum Time Interval Error of TOUT0 output port 10 T im e (ns) 1 G .8 13 optio n 1 con s tan t tem perature w ander lim it 0 .1 T D E V m ea su rem e nt on 1 55 M H z ou tpu t, 19.44 M H z i/p (8kH z locking), V ectron 6 664 xtal 0.01 0.01 0.1 1 10 1 00 1 000 100 00 O bs erva tio n interval (s ) Figure 5: Time Deviation of TOUT0 output port 10000000 1000000 Phase Error (ns) P e rm itte d P h a s e E rro r L im it 100000 10000 T y p ic a l m e a s u re m e n t, 2 5 C c o n s ta n t te m p e ra tu re 1000 100 1000 10000 100000 Figure 6: Phase error accumulation of TOUT0 output port in Holdover mode Revision 2.05/Jan 2001 a2001 Semtech Corp 14 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS during category(b) operation (interpreted as being applicable to Holdover mode operation) be limited to less than 30 slips (of 125 s each) per hour ((((60 x 60)/30)+125s)/(60x60)) = 1.042 ppm. FINAL is enabled. When PBO is enabled, it can also be frozen, which will disable the PBO operation on the next input reference switch, but will remain with the current offset. If PBO is disabled while the device is in the Locked mode, there will be a phase jump on the output SEC clocks as the DPLL locks back to 0 degree phase error. Phase Build Out Phase Transient response and Holdover Phase Build Out (PBO) is the function to minimise phase transients on the output SEC clock during input reference switching or mode switching. If the currently selected input reference clock source is lost (due to a short interruption, out of frequency detection, or complete loss of reference), the second, next highest priority reference source will be selected. During this transition, the Lost_Phase mode is entered. The typical phase disturbance on clock reference source switching will be less than 10 ns on the ACS8515. For clock reference switching caused by the main input failing or being disconnected, then the phase disturbance on the output will still be less than the 120 ns allowed for in the G.813 spec. The actual value is dependant on the frequency being locked to. The PBO requirement, as specified in Telcordia GR1244-CORE, Section 5.7, in that a phase transient of greater than 3.5 s occuring in less than 0.1 seconds should be absorbed, will be implemented on a future version. ITU-T G.813 states that the max allowable short term phase transient response, resulting from a switch from one clock source to another, with Holdover mode entered in between, should be a maximum of 1 s over a 15 second interval. The maximum phase transient or jump should be less than 120 ns at a rate of change of less than 7.5 ppm and the Holdover performance should be better than 0.05 ppm. On the ACS8515, PBO can be enabled, disabled or frozen using the P interface. By default, it Revision 2.05/Jan 2001 a2001 Semtech Corp 15 Micro-Processor Interface The ACS8515 incorporates a serial microprocessor interface that is compatible with the Serial Peripheral Interface (SPI) for device setup. Register Set All registers are 8-bits wide, organised with the most-significant bit positioned in the left-most bit, with bit-significance decreasing towards the right-most bit. Some registers carry several individual data fields of various sizes, from single-bit values (e.g., flags) upwards. Several data fields are spread across multiple registers; their organisation is shown in the register map. Configuration Registers Each configuration register reverts to a default value on power-up or following a reset. Most default values are fixed, but some will be pinsettable. All configuration registers can be read out over the microprocessor port. Status Registers The Status Registers contain readable registers. They may all be read from outside the chip but are not writable from outside the chip (except for a clearing operation). All status registers are read via shadow registers to avoid data hits due to dynamic operation. Each individual status register has a unique location. www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS Register Access FINAL Any unmasked bit set in the interrupt status register will cause the interrupt request pin to be asserted (high). All interrupts are cleared by writing a '1' to the bit(s) to be cleared in the status register. When all pending unmasked interrupts are cleared the interrupt pin will go inactive (low). The loss of the currently selected reference source will eventually cause the input to be considered invalid, triggering an interrupt. The time taken to raise this interrupt is dependant on the leaky bucket configuration of the activity monitors. The very fastest leaky bucket setting will still take up to 128 ms to trigger the interrupt. The interrupt caused by the brief loss of the currently selected reference source is provided to facilitate very fast source failure detection if desired. It is triggered after missing just a couple of cycles of the reference source. Some applications require the facility to switch downstream devices based on the status of the reference sources. In order to provide extra flexibility, it is possible to flag the "main reference failed" interrupt (addr 06, bit 6) on the pin TDO. This is simply a copy of the status bit in the interrupt register and is independent of the mask register settings. The bit is reset by writing to the interrupt status register in the normal way. This feature can be enabled and disabled by writing to bit 6 of register 48Hex. Most registers are of one of two types, configuration registers or status registers, the exceptions being the Chip_revision register. Configuration registers may be written to or read from at any time (the complete 8-bit register must be written, even if only one bit is being modified). All status registers may be read at any time and, in some status registers (such as the sts_interrupts register), any individual data field may be cleared by writing a "1" into each bit of the field (writing a "0" value into a bit will not affect the value of the bit). Details of each register are given in the Register Map and Register Description sections. Interrupt Enable and Clear Interrupt requests are flagged on pin INTREQ (active High). Bits in the interrupt status register are set (high) by the following conditions; (i) any reference source becoming valid or going invalid (ii) a change in the operating state (eg. Locked, Holdover etc.) (iii) brief loss of the currently selected reference source All interrupt sources are maskable via the mask register (cnfg_interrupt_mask), each one being enabled by writing a '1' to the appropriate bit. Revision 2.05/Jan 2001 a2001 Semtech Corp 16 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS Register map Shaded areas in the map are dont care and writing either 0 or 1 will not affect any function of the device. Bits labelled Set to 0 or Set to 1 must be set as stated during initialisation of the device, either following power up, or after a power on reset (POR). Failure to correctly set these bits may result in the device operating in an unexpected way. Some registers do not appear in this list, for example 07 and 08. These are either not used, or have test functionality. Do not write to any undefined registers as this may cause the device to operate in a test mode. If an undefined register has been inadvertently addressed, the device should be reset to ensure the undefined registers are at default values. FINAL A d d r. P ar am et er N am e ( Hex ) 7 ( m sb ) 02 03 04 05 06 09 0A 0B 0C 0D 07 0E 0F 11 12 14 sts_reference_sources (read/w rite) status D at a B i t 6 5 4 3 2 1 0 ( l sb ) Chip revision numb er (7:0) Analog div sync Phase loss flag limit SEC1DIFF SEC2 Set to '0' Set to '0' Set to '0' SEC1 SEC3 Op erating mode (2:0) Currently selected reference source 2nd highest p riority valid source Set to '0' Set to '1' Set to '0' Set to '0' Current increment offset (7:0) Current increment offset (15:8) Current increment offset (18:16) SEC1DIFF SEC2 SEC1 SEC3 status Revision 2.05/Jan 2001 a2001 Semtech Corp 17 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS A d d r. P ar am et er N am e ( Hex ) 7 ( m sb ) 18 19 1A 1B 1C 1D 1E 22 23 24 25 28 32 33 34 cnfg_op erating_mode (read/w rite) cnfg_ref_selection (read/w rite) cnfg_mode (read/w rite) A u to external 2k enab le Phase alarm timeout enab le Clock edge Holdover offset enab le Set to '0' SEC2DIFF PECL 311.04 MHz on O1 1=SON ET 0=SDH for Dig1 Set to '0' Set to '0' O2 Set to '0' SEC1DIFF PECL Set to '0' External 2k Sync enab le cnfg_ref_source_frequency (read/w rite) Set to '0' Set to '0' Set to '0' Set to '0' divn divn divn divn divn cnfg_ref_selection_p riority (read/w rite) Set to '0' FINAL D at a B i t 6 Set to '0' 5 Set to '0' 4 Set to '0' 3 Set to '0' 2 Set to '0' 1 Set to '0' 0 ( l sb ) Set to '0' p rogrammed _p riority p rogrammed _p riority p rogrammed _p riority b ucket_id reference_source_frequency SON ET/ SDH I/P reversion mode 35 36 38 cnfg_control3 (read/w rite) cnfg_differential_inp uts (read/w rite) cnfg_outp ut_enab le (read/w rite) cnfg_O1_outp ut_frequencies (read/w rite) cnfg_differential_outp ut (read/w rite) cnfg_b andw idth (read/w rite) cnfg_nominal_frequency (read/w rite) Auto b /w sw itch acq/lock Set to '0' 39 3A 3B Digital 1 O1 frequency selection Set to '0' Set to '0' O1 LVDS enab le O1 PECL enab le Acquistion b andw idth Set to '0' N ormal/locked b andw idth 3C 3D N ominal frequency (7:0) N ominal frequency (15:8) Revision 2.05/Jan 2001 a2001 Semtech Corp 18 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS FINAL A d d r. P ar am et er N am e ( Hex ) 7 ( m sb ) 3E 3F 40 A u to Holdover Averaging cnfg_freq_limit (read/w rite) cnfg_holdover_offset (read/w rite) D at a B i t 6 5 4 3 2 1 0 ( l sb ) Holdover offset (7:0) Holdover offset (15:8) Holdover offset (18:16) DPLL Frequency offset limit (7:0) DPLL Frequency offset limit (9:8) 41 42 43 44 45 46 47 48 cnfg_interrup t_mask (read/w rite) Set to '0' Op er. mode Set to '0' Main ref status SEC2DIFF Set to '0' status SEC1DIFF Set to '0' Set to '0' status SEC2 Set to '0' Set to '0' status SEC1 Set to '0' Set to '0' Set to '0' Set to '0' Set to '0' Set to '0' status SEC3 Set to '0' cnfg_freq_divn (read/w rite) Divide-inp ut-b y-n ratio (7:0) Divide-inp ut-b y-n ratio (13:8) cnfg_monitors (read/w rite) Flag ref lost on TDO Ultra-fast sw itching External source sw itch enab le Freeze p hase b uildout Phase b uildout enab le Frequency monitors configuration (1:0) 50 51 52 53 54 55 56 57 58 59 cnfg_activ_up p er_threshold 0 (read/w rite) cnfg_activ_low er_threshold 0 (read/w rite) cnfg_b ucket_size 0 (read/w rite) cnfg_decay_rate 0 (read/w rite) cnfg_activ_up p er_threshold 1 (read/w rite) cnfg_activ_low er_threshold 1 (read/w rite) cnfg_b ucket_size 1 (read/w rite) cnfg_decay_rate 1 (read/w rite) cnfg_activ_up p er_threshold 2 (read/w rite) cnfg_activ_low er_threshold 2 (read/w rite) Configuration 0: Activity alarm set threshold (7:0) Configuration 0: Activity alarm reset threshold (7:0) Configuration 0: Activity alarm b ucket size (7:0) Configuration 0: decay_rate (1:0) Configuration 1: Activity alarm set threshold (7:0) Configuration 1: Activity alarm reset threshold (7:0) Configuration 1: Activity alarm b ucket size (7:0) Configuration 1: decay_rate (1:0) Configuration 2: Activity alarm set threshold (7:0) Configuration 2: Activity alarm reset threshold (7:0) Revision 2.05/Jan 2001 a2001 Semtech Corp 19 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS A d d r. P ar am et er N am e ( Hex ) 7 ( m sb ) 5A 5B 5C 5D 5E 5F cnfg_b ucket_size 2 (read/w rite) cnfg_decay_rate 2 (read/w rite) cnfg_activ_up p er_threshold 3 (read/w rite) cnfg_activ_low er_threshold 3 (read/w rite) cnfg_b ucket_size 3 (read/w rite) cnfg_decay_rate 3 (read/w rite) Configuration 3: Activity alarm set threshold (7:0) Configuration 3: Activity alarm reset threshold (7:0) Configuration 3: Activity alarm b ucket size (7:0) Configuration 3: decay_rate (1:0) FINAL D at a B i t 6 5 4 3 2 1 0 ( l sb ) Configuration 2: Activity alarm b ucket size (7:0) Configuration 2: decay_rate (1:0) Register map description A d d r. P ar am et er N am e ( Hex ) 02 03 ch ip _revision cnfg_control1 D e scr i p t i o n Th is read only register contains th e ch ip revision numb er Bits (3:0) & 5 are test controls and must b e eith er set at '0' d uring initialisation or left unch anged . Bit 4, w h en set h igh , synch ronises th e d ivid ers in th e outp ut A PLL section to th e d ivid ers in th e DPLL section such th at th eir p h ases align. Th is is necessary to h ave th e p h ase alignment b etw een th e inp uts and outp ut clocks at OC3 d erived rates (6.48 MHz to 77.76 MHz). By d efault, synch ronisation occurs for 2 second s after p ow er up and is th en turned off. Setting th is b it h igh keep s synch ronisation on, w h ich may b e necessary to avoid th e d ivid ers getting out of sync w h en q uick ch anges in freq uency occur such as a force into freerun mod e. D e f au l t Val u e ( b i n ) 00000001 XX000000 04 cnfg_control2 Bits (2:0) are test controls and must b e set at '010' d uring initialisation or left unch anged . Bits (5:3) d efine th e p h ase loss flag limit. By d efault set to 4 (100) w h ich corresp ond s to ap p roximately 140. A low er value sets a corresp ond ing low er p h ase limit. Th e flag limit d etermines th e value at w h ich th e DPLL ind icates p h ase lost as a result of inp ut jitter, a p h ase jump , or a freq uency jump on th e inp ut XX100010 sts_interrup ts Th is 16 b it register contains one b it for each b it of sts_sources_valid , one for loss of reference th e d evice w as locked to, and anoth er for th e op erating mod e. A ll b its are active h igh . A ll b its excep t th e 'main ref failed ' b it (b it 14) are set on a "ch ange" in th e state of th e relevent status b it, i.e. if a source b ecomes valid , or goes invalid it w ill trigger an interrup t. If th e Op erating Mod e (register 9) ch anges state th e interrup t w ill b e generated . Bit 14 (main ref failed ) of th e interrup t status register is used to flag inactivity on th e reference th at th e d evice is locked to much more q uickly th an th e activity monitors can sup p or t. If b it 6 of th e cnfg_monitors register (register 48) (flag ref loss on TDO) is set, th en th e state of th is b it is d riven onto th e TDO p in of th e d evice. A ll b its are maskab le b y th e b its in th e cnfg_interrup t_mask register. Each b it may b e cleared ind ivid ually b y w riting a '1' to th at b it, th us resetting th e interrup t. A ny numb er of b its can b e cleared w ith a single w rite op eration. Writing '0's w ill h ave no effect. 05 Bits (7:6) unused Least significant b yte (5:2) Bits (1:0) unused . Most significant b yte (7:6) and 0 Bits (5:1) unused XX0000XX 06 00XXXXX0 Revision 2.05/Jan 2001 a2001 Semtech Corp 20 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS A d d r. P ar am e t e r N am e ( Hex ) 09 sts_op erating_mode FINAL D e scr i p t i o n D e f au l t Val u e ( b i n ) XXXXX001 Th is read -only register h old s th e current op erating state of th e main state mach ine. Figure 7 sh ow h ow th e values of th e 'op erating state' variab le match w ith th e ind ivid ual states. B it Content 2:0 Op erating state (2:0) Bits (2:0) State 001 freerun 010 h old over 100 locked 110 p re-locked 101 p re-locked 2 111 p h ase lost 3:7 unused sts_p riority_tab le Th is is a 16-b it read -only register, taking tw o ad d resses. Currently-selected reference source: th is is th e ch annel numb er of th e inp ut reference source w h ich is currently connected to th e SETG function. High est-p riority valid source: th is is th e ch annel numb er of th e inp ut reference source w h ich is valid and h as th e h igh est p riority; it may not b e th e same as th e currently-selected reference source (d ue to failure h istory or ch anges in p rogrammed p riority). Second -h igh est p riority valid source: th is is th e ch annel numb er of th e inp ut reference source w h ich is valid and h as th e next-h igh est p riority to th e h igh est-p riority valid source. Th ird -h igh est p riority valid source: th is is th e ch annel numb er of th e inp ut reference source w h ich is valid and h as th e next-h igh est p riority to th e second -h igh est-p riority valid source. N ote th at th ese registers are up d ated b y th e state mach ine in resp onse to th e contents of th e cnfg_ref_selection_p riority register and th e ongoing status of ind ivid ual ch annels; ch annel numb er '0000', ap p earing in any of th ese registers, ind icates th at no ch annel is availab le for th at p riority. B it Content High est-p riority valid source Currently selected reference source 3rd-h igh est-p riority valid source 2nd-h igh est-p riority valid source 00000000 00000000 0A 0B sts_curr_inc_offset (7:4) (3:0) (7:4) (3:0) Th is read -only register contains a signed -integer value rep resenting th e 19 significant b its of th e current increment offset of th e d igital PLL. Th e register may b e read p eriod ically to b uild up a h istorical d atab ase for later use d uring h old over p eriod s (th is w ould only b e necessary if an external oscillator w h ich d id not meet th e stab ility criteria d escrib ed in Local Oscillator Clock section is used ). Th e register w ill read 00000000 immed iately after reset. Least significant b yte of offset value N ext significant b yte of offset value Bits (2:0) 3 most significant b its of offset value, b its (7:4) unused 00000000 00000000 XXXXX000 00000000 XX000000 Th is register only ind icates w h eth er or not a source h as p assed all criteria. 0C 0D 07 0E 0F sts_reference_sources sts_sources_valid Th is 8 b it register contains cop ies of b it 3 from all th e status_reference_sources b ytes. Th is allow s th e user to get th e valid ity of all sources in just 2 read s. Th is is a 5-b yte register w h ich h old s th e status of each of th e 8 inp ut reference sources. Th e status of each reference source is sh ow n in a 4-b it field . Each b it is active h igh .To aid status ch ecking, a cop y of each status b it 3 is p rovid ed in th e sts_sources_valid register. Th e status is rep or ted as follow s: (Each b it may b e cleared ind ivid ually) Status b it Status b it Status b it Status b it 0 = p h ase lock alarm 1 = no activity alarm 2 = out-of-b and alarm 3 = Source valid (no alarms) (b it 3 is comb ination of b its 0-2) Status of inp ut reference source SEC1 Status of inp ut reference source SEC2 Status of inp ut reference source SEC1DIFF Status of inp ut reference source SEC2DIFF 01100110 01100110 11 12 (3:0) (7:4) (3:0) (7:4) Revision 2.05/Jan 2001 a2001 Semtech Corp 21 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS A d d r. P ar am e t e r N am e ( Hex ) 14 sts_reference_sources cnfg_ref_selection_p riority (3:0) (7:4) FINAL D e scr i p t i o n D e f au l t Val u e ( b i n ) XXXX0110 Status of inp ut reference source SEC3 Unused Th is is a 7-b y te register w h ich h old s th e p riority of each of th e 3 inp ut reference sources. Th e p riority values are all relative to each oth er, w ith low er-valued numb ers taking h igh er p riorities. Only th e values 1 to 15(d ec) are valid - '0' d isab les th e reference source. Each reference source must b e given a uniq ue p riority. It is recommend ed to reserve th e p riority value '1' as th is is used w h en forcing reference selection via th e cnfg_ref_selection register. If th e user d oes not intend to use th e cnfg_ref_selection register th en p riority value '1' need not b e reserved . B it Content Must b e set to 00000000 d uring initialisation Programmed p riority of inp ut reference source SEC1 Programmed p riority of inp ut reference source SEC2 Programmed p riority of inp ut reference source SEC1DIFF Programmed p riority of inp ut reference source SEC2DIFF Must b e set to 00000000 d uring initialisation Programmed p riority of inp ut reference source SEC3 Must b e set to 0000 d uring initialisation Must b e set to 00000000 d uring initialisation Must b e set to 00000000 d uring initialisation 00110010 01010100 01110110 10011000 10111010 11010001 11111110 18 19 1A 1B 1C 1D 1E cnfg_ref_source_freq uency (7:0) (3:0) (7:4) (3:0) (7:4) (7:0) (3:0) (7:4) (7:0) (7:0) Th is is a 5-b y te register w h ich h old s th e key s to th e freq uencies of each of th e 5 inp ut reference sources, as listed b elow. Bits (3:0) d efine th e freq uency of th e reference source in accord ance w ith th e follow ing key : Value (3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Freq uency 8 kHz 1544 kHz(SON ET)/2048 kHz(SDH) (A s d efined b y Register 34, b it 2) 6.48 MHz 19.44 MHz 25.92 MHz 38.88 MHz 51.84 MHz 77.76 MHz 155.52 MHz 2 kHz 4 kHz Bits (5:4) togeth er d efine w h ich leaky b ucket settings (0-3) are used , as d efined in registers 50 (h ex)to 5F (h ex). Bits (7:6) of each b y te d efine th e op eration und er taken on th e inp ut freq uency, in accord ance w ith th e follow ing key : 00 01 10 11 Th e inp ut freq uency is fed d irectly into th e DPLL Th e inp ut freq uency is internally d ivid ed d ow n to 8 kHz, b efore b eing fed into th e DPLL. Th is gives excellent jitter tolerance. Unsup p or ted configuration - d o not use Uses th e d ivision coefficient stored in register cnfg_freq _d ivn to d ivid e th e inp ut b y th is value p rior to going to th e DPLL. Th e freq uency monitors must b e d isab led . Th e d ivid ed d ow n freq uency sh ould eq ual 8 kHz. Th e freq uency (3:0) sh ould b e set to th e nearest sp ot freq uency just b elow th e actual inp ut freq uency. Th e DivN feature w orks for inp ut freq uencies b etw een 1.544 MHz and 100 MHz. Freq uency of reference source SEC1 Freq uency of reference source SEC2 Freq uency of reference source SEC1DIFF Freq uency of reference source SEC2DIFF Freq uency of reference source SEC3 cnfg_op erating_mod e Th is 3-b it register is used to force th e d evice into a d esired op erating state, rep resented b y th e b inary values sh ow n in Figure 8. Value 0 (h ex) allow s th e control state mach ine to op erate automatically. B it (2:0) (7:3) Reference source Desired op erating state (as p er Figure 8) Unused 00000000 00000000 00000011 00000011 00000011 22 23 24 25 28 32 XXXXX000 Revision 2.05/Jan 2001 a2001 Semtech Corp 22 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS A d d r. P ar am et er N am e ( Hex ) 33 cnfg_ref_selection FINAL D e scr i p t i o n D e f au l t Val u e ( b i n ) This 4-b it register occup ies the entire 8-b it sp ace at address 33(hex). It is used to force the device to select a p ar ticular inp ut reference source, irresp ective of its p riority. Writing to this register temp orarily raises the selected inp ut to p riority '1'. Provided no other inp ut is already p rogrammed w ith p riority '1', and rever tive mode is on, this source w ill b e selected, if it has b een validated b y the frequency and activity monitors. Bit (3:0) define the source that is selected in accordance w ith the follow ing key. Bits (7:4) are unused. Writing X0(hex) or XF(hex) w ill disab le all inp ut reference sources. * The default is XF. Value (3:0) 0011 0100 0101 0110 1001 Selected source SEC1 SEC2 SEC1DIFF SEC2DIFF SEC3 XXXX1111* 34 cnfg_mode This 6-b it register occup ies the address 34(hex). It contains several individual configuration fields, as detailed b elow : B it 0 = 0 N on-rever tive Mode: The device w ill retain the p resently selected source. This is the default state. = 1 Rever tive Mode: The device w ill sw itch to the highest p riority source show n in sts_p riority_tab le register(7:4) (at address 0A(hex)). Bits 1 is unused. B it 2 =0 SDH mode: The device exp ects the inp ut frequency of any inp ut channel given the value '0001' in the cnfg_ref_source_frequency register to b e 2048 kHz. This b it is w riteab le. =1 SON ET mode: The device exp ects the inp ut frequency of any inp ut channel given the value '0001' in the cnfg_ref_source_frequency register to b e 1544 kHz. This b it is w riteab le. B it 3 =0 External 2 kHz Sync Disab le. The device w ill ignore the Sync2k p in. =1 External 2 kHz Sync Enab le. The device w ill align the p hase of its internally generated Frame Sync signal (8 kHz) and Multi-Frame Sync signal (2 kHz) w ith that of the signal sup p lied to the Sync2k p in. The device should b e locked to a 6.48 MHz outp ut from an ACS8510. This is the default state. B it 4 =0 Holdover offset disab le: The device w ill ignore the value and holdover w ill use the current PLL integral p ath value. This is the default state. =1 Holdover offset enab le: The device w ill adop t the Holdover offset value stored in the cngf_holdover_offset register. This value is then used to set the frequency in holdover mode. B it 5 =0 Falling Clock Edge selected: The device w ill reference to the falling edge of the external oscillator signal. This is the default state. =1 Rising Clock Edge selected: The device w ill reference to the rising edge of the external oscillator signal. B it 6 =0 Phase Alarm Timeout disab le: The p hase alarm w ill not timeout and must b e reset b y softw are. =1 Phase Alarm Timeout enab le: The p hase alarm w ill timeout after 100 seconds. This is the default state. B it 7 =0 Auto 2 kHz Sync Disab le. The user controls this function using b it 3 of this register, as describ ed ab ove. =1 Auto 2 kHz Sync Enab le. External 2 kHz Sync w ill b e enab led only w hen the source is locked to 6.38 MHz. Otherw ise it w ill b e disab led. This is the default state. 11001000 Revision 2.05/Jan 2001 a2001 Semtech Corp 23 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS A d d r. P ar am e t e r N am e ( Hex ) 36 cnfg_d ifferential_inp uts FINAL D e scr i p t i o n D e f au l t Val u e ( b i n ) Th is 2-b it register occup ies th e entire 8-b it sp ace at ad d ress 36(h ex). It contains tw o ind ivid ual configuration field s, as d etailed b elow : B it 0 1 (7:2) Configuration field '1' = Inp ut SEC1DIFF is PECL-comp atib le '0' = Inp ut SEC1DIFF is LV DS-comp atib le (Default) '1' = Inp ut SEC2DIFF is PECL-comp atib le (Default) '0' = Inp ut SEC2DIFF is LV DS-comp atib le Unused XXXXXX10 38 cnfg_outp ut_enab le Th is 8-b it register occup ies th e entire 8-b it sp ace at ad d ress 38(h ex). It contains several ind ivid ual configuration field s, as d etailed b elow : B it Configuration field 0, 1, 3, 4, 6 are unused , and sh ould b e set to '0' 2 5 7 '1' = Outp ut p or t O2 enab led '0' = Outp ut p or t O2 d isab led '1' = Sonet mod e selected for Dig1 '0' = SDH mod e selected for Dig1 '1' = O1 outp ut freq uency set to 311.04 MHz '0' = O1 outp ut freq uency set b y A d d ress 3A (5:4) 00011111 N ote: "Disab led " means th at th e outp ut p or t h old s a static logic value (th e p or t is not Tri-stated ). 39 cnfg_01_outp ut_freq uencies Th is register h old s th e freq uency selections for th e 01 outp ut p or t, as d etailed b elow. B it Configuration field (0:3) and (6:7) are unused (5:4) 00 01 10 11 * = d efault Dig1 freq uency 1544 kHz/2048 kHz* 3088 kHz/4096 kHz 6176 kHz/8192 kHz 12352 kHz/16384 kHz 00001000 For Dig1 th e left most freq uency values are for Sonet mod e and th e oth ers are for SDH mod e. Th ey are selected via th e SON ET/SDH b its in register cnfg_outp ut_enab le. 3A cnfg_d ifferential_outp uts Th is register h old s th e freq uency selections and th e p or t-tech nology typ e for th e d ifferential outp ut O1, as d etailed b elow. Bits 7, 6, 3 and 2 are unused . B it (1:0) 00 01 10 11 3B cnfg_b and w id th Configuration field B it PECL/LV DS (5:4) Por t d isab led 00 PECL-comp atib le 01 LV DS-comp atib le (d efault) 10 unused 11 Configuration field O1 freq uency 38.88 MHz (d efault) 19.44 MHz 155.52 MHz Dig1. XX00XX10 Th is register contains information used to control th e op eration of th e d igital PLL. Wh en b and w id th selection is set to automatic, th e DPLL w ill use th e acq uisition b and w id th setting w h en out of lock, and th e normal/locked b and w id th setting w h en in lock. Wh en set to manual, th e DPLL w ill alw ay use th e normal/locked b and w id th setting. Bit (2:0) 000 001 010 011 100 101 110 111 3 Loop b and w id th 0.1 Hz 0.3 Hz 0.6 Hz 1.2 Hz 2.5 Hz 5.0 Hz 10 Hz 20 Hz unused (6:4) 000 001 010 011 100 101 110 111 7 A cq uisition b and w id th 0.1 Hz 0.3 Hz 0.6 Hz 1.2 Hz 2.5 Hz 5.0 Hz 10 Hz 20 Hz Band w id th selection '0'= Manual op eration '1'= A utomatic op eration 0111X101 Revision 2.05/Jan 2001 a2001 Semtech Corp 24 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS A d d r. P ar am et er N am e ( Hex ) cnfg_nominal_frequency FINAL D e scr i p t i o n D e f au l t Val u e ( b i n ) This register holds a 16 b it unsigned integer rep resenting the desired nominal frequency. This is availab le to op tionally calib rate the nominal outp ut frequency to comp ensate against variation in the external crystal frequencies. Least significant b yte. 10011001 3C 3D Most significant b yte. cnfg_holdover_offset This 19-b it register uses addresses 3E(hex) to 40(hex). It holds a 19 b it signed integer, rep resenting the holdover offset value, w hich can b e used to set the holdover mode frequency w hen enab led via the holdover offset enab led b it in the cnfg_mode register. Least significant b yte. N ext significant b yte Most significant b its. Bit 7 is Auto Holdover Averaging enab le - default 1. This enab les the frequency average to b e taken from 32 samp les. One samp le taken every 32 seconds, after the frequency has b een confirmed to b e in-b and b y the frequency monitors, giving a 17 minute history of the currently locked to reference source for use in Holdover. cnfg_freq_limit This register holds a 10 b it unsigned integer rep resenting the p ull-in range of the DPLL. It should b e set according to the accuracy of crystal imp lemented in the ap p lication, using the follow ing formula; Frequency range +/- (p p m) = (cnfg_freq_limit x 0.0785)+0.01647 or cnfg_freq_limit = (Frequency range - 0.01647) / 0.0785 Default value w hen SRCSW is left unconnected or tied low is 9.2 p p m. Default value w hen SRCSW is high is the full range of around 80 p p m. 10011001 3E 3F 00000000 00000000 40 1XXXX000 41 Least significant b yte 42 (7:2) unused (1:0) Most significant b its 01110110 (SRCSW low ) 11111111 (SRCSW high) XXXXXX00 (SRCSW low ) XXXXXX11 (SRCSW high) 11111111 43 cnfg_interrup t_mask Each b it of this 21 b it register, if set to zero, w ill disab le the ap p rop riate interrup t source in the interrup t status register. 44 11111111 45 XXX11111 cnfg_freq_divn This 15 b it integer is used as the divisor for any inp ut to get the p hase locking frequency desired. Only active for inp uts w ith the divn b it set to 1. This w ill cause the inp ut frequency to b e divided b y (n+1) p rior to p hase comp arison. The reference_source_frequency b its should reflect the source frequency after the division b y (n+1). 46 least-significant b yte. 00000000 47 most-significant b its. XX000000 Revision 2.05/Jan 2001 a2001 Semtech Corp 25 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS A d d r. P ar am et er N am e ( Hex ) 48 cnfg_monitors FINAL D e scr i p t i o n D e f au l t Val u e ( b i n ) This 7 b it register allow s glob al configuration of monitors and control of p hase b uild out. Bits (1:0) are for configuring frequency monitors- 00 = off, 01 = 15p p m, others are reserved for future use. Bit 2 Phase b uildout en enab les p haseb uildout. If disab led, the DPLL w ill alw ays lock to 0 degrees. Bit 3 Freeze p hase b uildout (w hen p hase b uildout is enab led) w ill effectively disab le any future p hase b uildout events b ut remain w ith the current p hase offset. Bit 4 External p rotection sw itching enab les the SrcSw it p in to force the locking to either inp ut 4 or 3. Bit 5 Ultra-fast sw itching enab les the dp ll to raise an inactivity alarm on the currently selected source after missing only a few cycles. This w ill enab le very fast sw itching aw ay from the selected source in a p rotection typ e ap p lication. This is triggered b y the main_ref_failed interrup t mechanism. Bit 6 Flag reference loss on TDO w ill enab le the value of the main_ref_failed interrup t to b e driven out of the TDO p in of the device. * The default value given is valid w hen SRCSWT p in is left unconnected or tied low. If SRCSWT is tied high, the default value is 15 (hex). X0000101* 50 51 52 53 cnfg_activ_up p er_threshold 0 This 8 b it register sets the value in the leaky b ucket that causes the activity alarm to b e raised. cnfg_activ_low er_threshold 0 This 8 b it register sets the value in the leaky b ucket that causes the activity alarm to b e cleared. cnfg_b ucket_size 0 cnfg_decay_rate 0 This 8 b it register sets the maximum value that the leaky b ucket can reach given an inactive i n p u t. This 2 b it register controls the leak rate of the leaky b ucket. The fill-rate of the b ucket is +1 for every 128ms interval that has exp erienced some level of inactivity. The decay rate is p rogrammab le in ratios of the fill rate. The ratio can b e set to 1:1, 2:1, 4:1, 8:1 b y using values of 00, 01, 10, 11 resp ectively. How ever, these b uckets are not true leaky b uckets in nature. The b ucket stop s leaking w hen it is b eing filled. This means that the fill and decay rates can b e the same (00 = 1:1) w ith the net effect that an active inp ut can b e recognised at the same rate as an inactive one. 00000110 00000100 00001000 XXXXXX01 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F cnfg_activ_up p er_threshold 1 This 8 b it register sets the value in the leaky b ucket that causes the activity alarm to b e raised. cnfg_activ_low er_threshold 1 This 8 b it register sets the value in the leaky b ucket that causes the activity alarm to b e cleared. cnfg_b ucket_size 1 cnfg_decay_rate 1 This 8 b it register sets the maximum value that the leaky b ucket can reach given an inactive i n p u t. As for register 53(hex) b ut for b ucket 1. 00000110 00000100 00001000 XXXXXX01 00000110 00000100 00001000 XXXXXX01 00000110 00000100 00001000 XXXXXX01 cnfg_activ_up p er_threshold 2 This 8 b it register sets the value in the leaky b ucket that causes the activity alarm to b e raised. cnfg_activ_low er_threshold 2 This 8 b it register sets the value in the leaky b ucket that causes the activity alarm to b e cleared. cnfg_b ucket_size 2 cnfg_decay_rate 2 This 8 b it register sets the maximum value that the leaky b ucket can reach given an inactive i n p u t. As for register 53(hex) b ut for b ucket 2. cnfg_activ_up p er_threshold 3 This 8 b it register sets the value in the leaky b ucket that causes the activity alarm to b e raised. cnfg_activ_low er_threshold 3 This 8 b it register sets the value in the leaky b ucket that causes the activity alarm to b e cleared. cnfg_b ucket_size 3 cnfg_decay_rate 3 This 8 b it register sets the maximum value that the leaky b ucket can reach given an inactive i n p u t. As for register 53(hex) b ut for b ucket 3. Revision 2.05/Jan 2001 a2001 Semtech Corp 26 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS Selection Source of Input Reference Clock FINAL the higher priority source until instructed to do so by the software, by briefly setting the Revertive mode bit. When there is a reference available with higher priority than the selected reference, there will be NO change of reference source as long as the Non-Revertive mode remains on. This is the case even of there are lower priority references available or the currently selected reference fails. When the ONLY valid reference sources that are available have a lower priority than the selected reference, a failure of the selected reference will always trigger a switch-over regardless of whether Revertive or Non-revertive mode has been chosen. Automatic Control Selection Under normal operation, the input reference sources are selected automatically by an order of priority, where SEC1 is the highest priority, SEC2 is the second highest priority and SEC3 is the lowest priority. The priorities can be reassigned with external software. The SEC1 reference source has inputs via either a low speed TTL input port or a high speed PECL/ LVDS input port. Similarly, the SEC2 reference source has both a low speed TTL or a high speed PECL/LVDS input port. The SEC3 (standby) reference source only has provision via a low speed TTL input port. There is provision for one sync clock input via a TTL port. Whilst SEC1, SEC2 and SEC3 reference source inputs can all be active at the same time, only one of the TTL or PECL/LVDS input ports for the SEC1 and SEC2 reference sources may be used at any time, the inactive port is ignored, by setting the priority of that port to zero. Restoration of repaired reference sources is handled carefully to avoid inadvertent disturbance of the output clock. The ACS8515 has two modes of operation; Revertive and nonRevertive. In Revertive mode, if a re-validated (or newly validated) source has a higher priority than the reference source which is currently selected, a switch over will take place. Many applications prefer to minimise the clock switching events and choose Non-Revertive mode. In Non-Revertive mode , when a revalidated (or newly validated) source has a higher priority then the selected source will be maintained. The re-validation of the reference source will be flagged in the sts_sources_valid register and, if not masked, will generate an interrupt. Selection of the re-validated source can only take place under software control the software should briefly enable Revertive mode to affect a switch-over to the higher priority source. If the selected source fails under these conditions the device will still not select Revision 2.05/Jan 2001 a2001 Semtech Corp 27 When automatic selection is required, the 'cnfg_ref_selection' registers must be set to allzero. The configuration registers, 'cnfg_ref_selection_priority', held in the P port are organised as 5, 4-bit registers with each representing an input reference port. Unused ports should be given the value, '0000' in the relevant register to indicate they are not to be included in the priority table. On power-up, or following a reset, the whole of the configuration file will be defaulted to the values defined by Table 1. The selection priority values are all relative to each other, with lower-valued numbers taking higher priorities. Each reference source should be given a unique number, the valid values are 1 to 15(dec). A value of 0 disables the reference source. However if two or more inputs are given the same priority number those inputs will be selected on a first in, first out basis. If the first of two same priority number sources goes invalid the second will be switched in. If the first then becomes valid again, it becomes the second source on the first in, first out basis, and there will not be a switch. If a third source with the same priority number as the other two becomes valid, it joins the priority list on the same first in, first out basis. There is no implied priority based on the www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS channel numbers. FINAL events occur at a rate which is not sufficient to overcome the decay, the alarm will not be triggered. On the alarm-clearing side, if no defect events occur for a sufficient time, the amplitude will decay gradually and the alarm will be cleared when the amplitude falls below the alarmclearing threshold. The ability to decay the amplitude over time allows the importance of defect events to be reduced as time passes by. This means that, in the case of isolated events, the alarm will not be set, whereas, once the alarm becomes set, it will be held on until normal operation has persisted for a suitable time (but if the operation is still erratic, the alarm will remain set). The "leaky bucket" accumulators are programmable for size, alarm set & reset thresholds and decay rate. Each source is monitored over a 128 ms period. If, within a 128 ms period, an irregularity occurs that is not deemed to be due to allowable jitter/wander, then the accumulator is incremented. The accumulator will continue to increment up to the point that it reaches the programmed bucket size. The "fill rate" of the leaky bucket is, therefore, 8 units/second. The "leak rate" Activity Monitoring The ACS8515 has a combined inactivity and irregularity monitor. The ACS8515 uses a "leaky bucket" accumulator, which is a digital circuit which mimics the operation of an analog integrator, in which input pulses increase the output amplitude but die away over time. Such integrators are used when alarms have to be triggered either by fairly regular defect events, which occur sufficiently close together, or by defect events which occur in bursts. Events which are sufficiently spread out should not trigger the alarm. By controlling the alarmsetting threshold, the point at which the alarm is triggered can be controlled. The point at which the alarm is cleared depends upon the decay rate and the alarm-clearing threshold. On the alarm-setting side, if several events occur close together, each event adds to the amplitude and the alarm will be triggered quickly; if events occur a little more spread out, but still sufficiently close together to overcome the decay, the alarm will be triggered eventually. If inactivities/irregularities reference source bucket_size leaky bucket response programmable fall slopes upper_threshold lower_threshold (all programmable) alarm Figure 7: Inactivity and irregularity monitoring Revision 2.05/Jan 2001 a2001 Semtech Corp 28 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS of the leaky bucket is programmable to be in multiples of the fill rate (x1, x0.5, x0.25 and x0.125) to give a programmable leak rate from 8 units/sec down to 1 unit/sec. A conflict between trying to leak at the same time as a fill is avoided by preventing a leak when a fill event occurs. Disqualification of a non-selected reference source is based on inactivity, or on an out of band result from the frequency monitors. The currently selected reference source can be disqualified for phase, frequency, inactivity or if the source is outside the DPLL lock range. If the currently selected reference source is disqualified, the next highest priority, active reference source is selected. Restoration of repaired reference sources is handled carefully to aviod inadvertant disruption of the output clock. The ACS8515 operates in a Non-revertive mode by default. In this mode, if the restored reference source has a higher FINAL priority than the reference source which is currently selected, a switch-over to the restored source will not tale place automatically. A restored reference source will assume its correct place in the priority table but a switchover will only take place automatically upon failure of the currently selected source. It is possible to invoke a switch-over by external control or by enabling revertive mode. Ultra Fast Switching A reference source is normally disqualified after the leaky bucket monitor thresholds have been crossed. An option for a faster disqualification has been implemented, whereby if register 48H, bit 5 (Ultra Fast Switching), is set then a loss of activity of just a few reference clock cycles will set the no activity alarm and cause a reference switch. This can be chosen to cause an interrupt to occur instead of or as well as causing the reference switch. Leaky bucket timing The time taken to raise an inactivity alarm on a reference source that has previously been fully active (leaky bucket empty) will be: (cnfg_activ_upper_threshold N) 8 where N is the number of the relevent leaky bucket configuration. If an input is intermittently inactive then this time can be longer. The default setting of cnfg_activ_upper_threshold is 6, therefore the default time is 0.75 s. The time taken to cancel the activity alarm on a previously completely inactive reference source is calculated as: (cnfg_decay_rate N) 2 x ((cnfg_bucket_size N) - (cnfg_activ_lower_thrshold N)) secs 8 where N is the number of the relevent leaky bucket configuration in each case. The default setting are shown in the following: 1 2 x (8-4) = 1.0 s 8 secs Revision 2.05/Jan 2001 a2001 Semtech Corp 29 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS External Protection Switching Free-Run mode FINAL The Free-Run mode is typically used following a power-on-reset or a device reset before network synchronisation has been achieved. In the Free-Run mode, the timing and synchronisation signals generated from the ACS8515 are based on the Master clock frequency provided from the external oscillator and are not synchronised to an input reference source. The frequency of the output clock is a fixed multiple of the frequency of the external oscillator, and the accuracy of the output clock is equal to the accuracy of the Master clock. The transition from Free-Run to Pre-locked(1) occurs when the ACS8515 selects a reference source. Pre-Locked(1) mode Fast external switching between inputs SEC1 and SEC2 can also be triggered directly from a dedicated pin (SRCSW). This mode can be activated either by holding this pin high during reset, or by writing to bit 4 of register address 48Hex. Once external protection switching is enabled, then the value of this pin directly selects either SEC1 (SRCSW high) or SEC2 (SRCSW low). If this mode is activated at reset by pulling the SRCSW pin high, then it configures the default frequency tolerance of SEC1 and SEC2 to +/80 ppm (register address 41Hex and 42Hex). Any of these registers can be subsequently set by external s/w if required. When external protection switching is enabled, the device will operate as a simple switch. All clock monitoring is disabled and the DPLL will simply be forced to try to lock on to the indicated reference source. The operating state (sts_operating_mode register) will always indicate locked in the mode. The ACS8515 will enter the Locked state in a maximum of 100 seconds, as defined by GR1244-CORE specification, if the selected reference source is of good quality. If the device cannot achieve lock within 100 seconds, it reverts to Free-Run mode and another reference source is selected. Locked mode Modes of Operation The ACS8515 has three primary modes of operation (Free-Run, Locked and Holdover) supported by three secondary, temporary modes (Pre-Locked, Lost_Phase and PreLocked2). These are shown in the State Transition Diagram, Figure 6. The ACS8515 can operate in Forced or Automatic control. On reset, the ACS8515 reverts to Automatic Control, where transitions between states are controlled completely automatically. Forced Control can be invoked by configuration, allowing transitions to be performed under external control. This is not the normal mode of operation, but is provided for special occasions such as testing, or where a high degree of hands-on control is required. Revision 2.05/Jan 2001 a2001 Semtech Corp 30 The Locked mode is used when an input reference source has been selected and the PLL has had time to lock. When the Locked mode is achieved, the output signal is in phase and locked to the selected input reference source. The selected input reference source is determined by the priority table. When the ACS8515 is in Locked mode, the output frequency and phase follows that of the selected input reference source. Variations of the external crystal frequency have a minimal effect on the output frequency. Only the minimum to maximum frequency range is affected. Note that the term, 'in phase', is not applied in the conventional sense when the ACS8515 is used as a frequency translator (e.g., when the input frequency is 2.048MHz and www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS the output frequency is 19.44 MHz) as the input and output cycles will be constantly moving past each other; however, this variation will itself be cyclical over time unless the input and output are not locked. Lost_Phase mode FINAL due to temperature fluctuations in the room, then the instantaneous value can be different from the average value, and then it may be possible to exceed the 0.05 ppm limit (depending on how extreme the temperature fluctuations are). It is advantageous to shield the TCXO to slow down frequency changes due to drift and external temperature fluctuations. In Holdover mode, the ACS8515 provides the timing and synchronisation signals to maintain the Network Element (NE), but they are not phase locked to any input reference source. The timing is based on a stored value of the frequency ratio obtained during the last Locked mode period. The frequency accuracy of Holdover mode has to meet the ITU-T, ETSI and Telcordia performance requirements. The performance of the external oscillator clock is critical in this mode, although only the frequency stability is important - the stability of the output clock in Holdover is directly related to the stability of the external oscillator. Pre-Locked(2) mode Lost_Phase mode is used whenever the selected reference source suffers most kinds of anomalous behaviour. Clock generation is performed in the same way as in the Holdover mode. If the leaky bucket accumulator calculates that the anomaly is serious, the device rejects the reference source and one of the following transitions takes place: Go to Pre-Locked(2); - If a known-good standby source is available. Go to Holdover; - If no standby sources are available. Holdover mode The Holdover mode is used when the circuit was in Locked mode but the selected reference source has become unavailable and a replacement has not yet been selected. The Holdover performance is mainly limited by what is happening to the TCXO. The ACS8515 has 3 ways of determining Holdover, either; 1. By external frequency setting (cnfg_holdover_offset register) 2. By an internal frequency measuring and averaging system which averages the last 20 minutes 3. By just using the last frequency (as reported by the sts_curr_inc_offset register). This value can be read out of the device and used to build up a longer term average using an external averaging circuit. This value can then to readback into the device and used as the Holdover offset (via cnfg_holdover_offset register). This state is very similar to the Pre-Locked(1) state. It is entered from the Holdover state when a reference source has been selected and applied to the phase locked loop. It is also entered if the device is operating in revertive mode and a higher-priority reference source is restored. PORB The Power On Reset (PORB) pin resets the device if forced Low for a power-on-reset to be initiated. The reset is asynchronous, the minimum Low pulse width is 5 ns. Reset is needed to initialize all of the register values to their defaults. Asserting Reset (POR) is required at power on, and may be re-asserted at any time to restore defaults. This is implemented www.semtech.com By default it uses the internal averager. This means that if the TCXO frequency is varying Revision 2.05/Jan 2001 a2001 Semtech Corp 31 ACS8515 LC/P ADVANCED COMMUNCIATIONS most simplistically by an external capacitor to GND along with the internal pull-up resistor. The ACS8510 is held in a reset state for 250 FINAL ms after the PORB pin has been pulled High. In normal operation PORB should be held High. (1)Reset free-run select ref (state 001) (3) no valid standby ref & (main ref invalid or out of lock >100s) (2) all refs evaluated & at least one ref valid Reference sources are flagged as 'valid' when active, 'in-band' and have no phase alarm set. (4) valid standby ref & [ main ref invalid or (higher-priority ref valid & in revertive mode) or out of lock >100s] pre-locked w ait for up to 100s (state 110) All sources are continuously checked for activity and frequency. Only the main source is checked for phase. A phase lock alarm is only raised on a reference when that reference has lost phase whilst being used as the main reference. The micro-processor can reset the phase lock alarm. A source is considered to have phase locked when it has been continuously in phase lock for between 1 and 2 seconds (5) selected ref phase locked locked keep ref (state 100) (10) selected source phase locked (9) valid standby ref & [ main ref invalid or (higher-priority ref valid & in revertive mode) ] (6) no valid standby ref & main ref invalid (8) phase regained within 100s (7) phase lost on main ref pre-locked2 w ait for up to 100s (state 101) (12) valid standby ref & (main ref invalid or out of lock >100s) Lost phase w ait for up to 100s (state 111) (11) no valid standby ref & (main ref invalid or out of lock >100s) holdover select ref (state 010) (15) valid standby ref & [ main ref invalid or (higher-priority ref valid & in revertive mode) or out of lock >100s] (13) no valid standby ref & (main ref invalid or out of lock >100s) (14) all refs evaluated & at least one ref valid Figure 8: Automatic Mode Control State Diagram. Revision 2.05/Jan 2001 a2001 Semtech Corp 32 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS Electrical Specification Important Note: The "Absolute Maximum Ratings" are stress ratings only, and functional operation of the device at conditions other than those indicated in the "Operating Conditions" sections of this specification are not implied. Exposure to the absolute maximum ratings for an extended period may reduce the reliability or useful lifetime of the product. ABSOLUTE MAXIMUM RATINGS PA RA MET ER Sup p ly Voltage V DD, V D+, V A1+,V A2+ Inp ut Voltage (non-sup p ly p ins) Outp ut Voltage (non-sup p ly p ins) A mb ient Op erating Temp erature Range Storage Temp erature FINAL SYM B OL V DD V in Vout TA Tstor MIN -0.5 -40 -50 MA X 3.6 5.5 5.5 85 150 U N IT S V V V C C OPERATING CONDITIONS PA RA MET ER Pow er Sup p ly (d c voltage) V DD, V D+,VA 1+, VA 2+, V DD_DIFF Pow er Sup p ly (d c voltage) V DD5 A mb ient temp erature Range Typ ical - one 19 MHz outp ut Maximum - 190 mA b efore s/w initialisation, 150 mA after s/w intialisation SYM B OL V DD V DD5 TA IDD PTOT MIN 3.0 3.0 -40 - T YP 3.3 3.3/5.0 110 360 MA X 3.6 5.5 85 190/150 685 U N IT S V V C mA mW Sup p ly current Total p ow er d issip ation Across operating conditions, unless otherwise stated DC CHARACTERISTICS: TTL Input pad. PA R A M E T E R V in High Vin Low Inp ut current SYM B OL V ih V il Ii n MIN 2.0 33 T YP - MA X 0.8 10 U N IT S V V A www.semtech.com Revision 2.05/Jan 2001 a2001 Semtech Corp ACS8515 LC/P ADVANCED COMMUNCIATIONS DC CHARACTERISTICS: TTL Input pad with internal pull-up. Across operating conditions, unless otherwise stated FINAL PA R A M E T E R V in High Vin Low Pull-up resistor Inp ut current SYM B OL V ih V il PU Ii n MIN 2.0 30 - T YP - MA X 0.8 80 120 U N IT S V V kW A DC CHARACTERISTICS: TTL Input pad with internal pull-down. Across operating conditions, unless otherwise stated PA R A M E T E R V in High Vin Low Pull-ud ow n resistor Inp ut current SYM B OL V ih V il PD Ii n MIN 2.0 30 - T YP - MA X 0.8 80 120 U N IT S V V kW A DC CHARACTERISTICS: TTL Output pad. Across operating conditions, unless otherwise stated PA R A M E T E R Vout Low Iol = 4mA Vout High Ioh = 4mA Drive current SYM B OL Vol Voh ID MIN 0 2.4 - T YP - MA X 0.4 U N IT S V V 4 mA Revision 2.05/Jan 2001 a2001 Semtech Corp 34 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS DC CHARACTERISTICS: PECL Input/Output pad. Across operating conditions, unless otherwise stated FINAL PA R A M E T E R PECL Inp ut Low voltage Differential inp uts (N ote 1) Differential inp uts (N ote 1) SYM B OL V ILPECL V IHPECL V IDPECL V ILPECL_S V IHPECL_S IIHPECL MIN V DD-2.5 V DD-2.4 0.1 V DD-2.4 V DD-1.3 T YP - MA X V DD-0.5 V DD-0.4 1.4 V DD-1.5 V DD-0.5 U N IT S V V V V V PECL Inp ut High voltage Inp ut Differential voltage PECL Inp ut Low voltage Single end ed inp ut (N ote 2) Single end ed inp ut (N ote 2) PECL Inp ut High voltage Inp ut High current Inp ut d ifferential voltage V ID = 1.4v Inp ut d ifferential voltage V ID = 1.4v (N ote 3) (N ote 3) -10 - +10 A Inp ut Low current IILPECL V OLPECL V OHPECL V ODPECL -10 - +10 A PECL Outp ut Low voltage PECL Outp ut High voltage PECL Outp ut Differential voltage (N ote 1) V DD-2.10 V DD-1.25 580 - V DD-1.62 V DD-0.88 900 V V mV Notes: Unused differential input ports should be left floating and set in LVDS mode, or the positive and negative inputs tied to VDD and GND respectively. Note 1. Assuming a differential input voltage of at least 100 mV. Note 2. Unused differential input terminated to VDD-1.4v. Note 3. With 50W load on each pin to VDD-2v. i.e. 82W to GND and 130W to VDD. Revision 2.05/Jan 2001 a2001 Semtech Corp 35 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS VDD 130R 130R ZO=50 FINAL VDD 8kHz, 1.544/2.048, 6.48, 19.44, 38.88, 51.84, 77.76 or 155.52 MHz ZO=50 I5POS ZO=50 82R 130R T06POS ZO=50 82R 130R 19.44, 38.88, 155.52, 311.04 MHz & DIG1 I5NEG 82R T06NEG 82R GND GND VDD 130R 130R ZO=50 ZO=50 VDD 8kHz, 1.544/2.048, 6.48, 19.44, 38.88, 51.84, 77.76 or 155.52 MHz I6POS ZO=50 82R 130R T07POS ZO=50 82R 130R 19.44, 51.84, 77.76, 155.52 MHz I6NEG 82R T07NEG 82R GND GND Recommended line termination for PECL Input/Output ports for VDD = 3.3V DC CHARACTERISTICS: LVDS Input/Output pad. Across operating conditions, unless otherwise stated PA R A M E T E R LV DS Inp ut voltage range Differential inp ut voltage = 100 mV SYM B OL V VRLVDS V DITH V IDLVDS MIN 0 -100 0.1 T YP - MA X 2.40 +100 1.4 U N IT S V mV V LV DS Differential inp ut th resh old LV DS Inp ut Differential voltage LV DS Inp ut termination resistance Must b e p laced externally across th e LV DS+/- inp ut p ins of A CS8510. Resistor sh ould b e 100W w ith 5% tolerance (N ote 1) (N ote 1) (N ote 1) R T E RM 95 100 105 W LV DS Outp ut h igh voltage LV DS Outp ut low voltage LV DS Differential outp ut voltage LV DS Ch arge in magnitud e of d ifferential outp ut voltage for comp limentary states (N ote 1) V OHLVDS V OLLVDS V ODLVDS 0.885 250 - 1.585 450 V V mV V DOSLVDS - - 25 mV LV DS outp ut offset voltage Temp erature = 25C (N ote 1) V OSLVDS 1.125 - 1.275 V Note 1. With 100W load between the differential outputs. Revision 2.05/Jan 2001 a2001 Semtech Corp 36 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS FINAL 8kHz, 1.544/2.048, 6.48, 19.44, 38.88, 51.84, 77.76 or 155.52 MHz ZO=50 ZO=50 I5POS ZO=50 100R T06POS ZO=50 100R 19.44, 38.88, 155.52, 311.04 MHz & DIG1 I5NEG T06NEG 8kHz, 1.544/2.048, 6.48, 19.44, 38.88, 51.84, 77.76 or 155.52 MHz ZO=50 ZO=50 I6POS ZO=50 100R T07POS ZO=50 100R 19.44, 51.84, 77.76, 155.52 MHz I6NEG T07NEG Recommended line termination for LVDS Input/Output ports Across operating conditions, unless otherwise stated DC CHARACTERISTICS: Output Jitter Generation Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8MHz TCXO on ICT Flexacom + 10MHz reference from Wavetek 905. Te s t d e f i n i t i o n G813 for 155.52 MHz op tion 1 G813 for 155.52 MHz op tion 1 F i l t e r u se d 500 Hz to 1.3 MHz 65 kHz to 1.3 MHz U I sp e c UIpp = 0.5 UIpp = 0.1 U I m e asu r e m e n t o n A C S 8515 R ev 2 0.058 (N ote 2) 0.048 (N ote 3) 0.048 (N ote 2) 0.053 (N ote 4) 0.053 (N ote 5) 0.058 (N ote 6) 0.053 (N ote 7) 0.053 (N ote 2) 0.058 (N ote 3) 0.057 (N ote 8) 0.055 (N ote 9) 0.057 (N ote 10) 0.057 (N ote 11) 0.057 (N ote 12) 0.053 (N ote 13) G813 & G812 for 2.048 MHz op tion 1 20 Hz to 100 kHz 37 G813 for 155.52 MHz op tion 2 12 kHz to 1.3 MHz UIpp = 0.1 UIpp = 0.05 0.046 (N ote 14) www.semtech.com Revision 2.05/Jan 2001 a2001 Semtech Corp ACS8515 LC/P ADVANCED COMMUNCIATIONS FINAL Te s t d e f i n i t i o n G812 for 1.544 MHz G812 for 155.52 MHz electrical G812 for 2.048 MHz electrical F i l t e r u se d 10 Hz to 40 kHz 500 Hz to 1.3 MHz 65 kHz to 1.3 MHz U I sp e c UIpp = 0.05 UIpp = 0.5 U Ip p = 0.075 U I m e asu r e m e n t o n A C S 8515 R ev 2 0.036 (N ote 14) 0.058 (N ote 3) 0.048 (N ote 3) Te s t d e f i n i t i o n ETS-300-462-3 for 2.048 MHz SEC ETS-300-462-3 for 2.048 MHz SEC (Filter sp ec 49 Hz to 100 kHz) ETS-300-462-3 for 2.048 MHz SSU ETS-300-462-3 for 155.52 MHz ETS-300-462-3 for 155.52 MHz F i l t e r u se d 20 Hz to 100 kHz U I sp e c UIpp = 0.5 U I m e asu r e m e n t o n A C S 8515 R ev 2 0.046 (N ote 14) 20 Hz to 100 kHz UIpp = 0.2 0.046 (N ote 14) 20 Hz to 100 kHz 500 Hz to 1.3 MHz 65 kHz to 1.3 MHz UIpp = 0.05 UIpp = 0.5 UIpp = 0.1 0.046 (N ote 14) 0.058 (N ote 3) 0.048 (N ote 3) Revision 2.05/Jan 2001 a2001 Semtech Corp 38 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS FINAL Te s t d e f i n i t i o n GR-253-CORE net i/f, 51.84 MHz GR-253-CORE net i/f, 51.84 MHz (Filter sp ec 20 kHz to 400 kHz) GR-253-CORE net i/f, 155.52 MHz GR-253-CORE net i/f, 155.52 MHz GR-253-CORE cat II elect i/f, 155.52 MHz F i l t e r u se d 100 Hz to 400 kHz U I sp e c UIpp = 1.5 U I m easu r em en t on A C S 8515 R ev 2 0.022 (N ote 3) 18 kHz to 400 kHz UIpp = 0.15 0.019 (N ote 3) 500 Hz to 1.3 MHz 65 kHz to 1.3 MHz UIpp = 1.5 UIpp = 0.15 UIpp = 0.1 UIrms = 0.01 UIpp = 0.1 UIrms = 0.01 UIpp = 0.1 UIrms = 0.01 0.058 (N ote 3) 0.048 (N ote 3) 0.058 (N ote 3) 0.006 (N ote 3) 0.017 (N ote 3) 0.003 (N ote 3) 0.036 (N ote 14) 0.0055 (N ote 14) 12 kHz to 1.3 MHz GR-253-CORE cat II elect i/f, 51.84 MHz 12 kHz to 400 kHz GR-253-CORE DS1 i/f, 1.544 MHz 10 Hz to 40 kHz Te s t d e f i n i t i o n AT&T 62411 for 1.544 MHz (Filter sp ec 10 Hz to 8 kHz) AT&T 62411 for 1.544 MHz AT&T 62411 for 1.544 MHz AT&T 62411 for 1.544 MHz F i l t e r u se d 10 Hz to 40 kHz 10 Hz to 40 kHz 10 Hz to 40 kHz Broad b and U I sp e c UIrms = 0.02 UIrms = 0.025 UIrms = 0.025 UIrms = 0.05 U I m e asu r e m e n t o n A C S 8515 R ev 2 0.0055 (N ote 14) 0.0055 (N ote 14) 0.0055 (N ote 14) 0.0055 (N ote 14) Revision 2.05/Jan 2001 a2001 Semtech Corp 39 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS Te s t d e f i n i t i o n G-742 for 2.048 MHz G-742 for 2.048 MHz (Filter sp ec 18 kHz to 100 kHz) G-742 for 2.048 MHz F i l t e r u se d DC to 100 kHz 20 Hz to 100 kHz 20 Hz to 100 kHz U I sp ec UIpp = 0.25 UIpp = 0.05 UIpp = 0.05 FINAL U I m easu r em en t on A C S 8515 R ev 2 0.047 (N ote 14) 0.046 (N ote 14) 0.046 (N ote 14) Te s t d e f i n i t i o n TR-N WT-000499 & G824 for 1.544 MHz TR-N WT-000499 & G824 for 1.544 MHz (Filter sp ec 8 kHz to 40 kHz) Te s t d e f i n i t i o n GR-1244-CORE for 1.544 MHz F i l t e r u se d 10 Hz to 40 kHz U I sp e c UIpp = 5.0 U I m easu r em en t on A C S 8515 R ev 2 0.036 (N ote 14) 10 Hz to 40 kHz UIpp = 0.1 0.036 (N ote 14) F i l t e r u se d >10 Hz U I sp e c UIpp = 0.05 U I m e asu r e m e n t o n A C S 8515 R ev 2 0.036 (N ote 14) Notes for the output jitter generation tables Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Note 7. Note 8. Note 9. Note 10. Note 11. Note 12. Note 13. Note 14. Filter used is that defined by test definition unless otherwise stated 5 Hz bandwidth, 19.44 MHz input, direct lock 5 Hz bandwidth, 19.44 MHz input, 8 kHz lock 20 Hz bandwidth, 19.44 MHz input, direct lock 20 Hz bandwidth, 19.44 MHz input, 8 kHz lock 10 Hz bandwidth, 19.44 MHz input, direct lock 10 Hz bandwidth, 19.44 MHz input, 8 kHz lock 2.5 Hz bandwidth, 19.44 MHz input, direct lock 2.5 Hz bandwidth, 19.44 MHz input, 8 kHz lock 1.2 Hz bandwidth, 19.44 MHz input, direct lock 1.2 Hz bandwidth, 19.44 MHz input, 8 kHz lock 0.6 Hz bandwidth, 19.44 MHz input, direct lock 0.6 Hz bandwidth, 19.44 MHz input, 8 kHz lock 5 Hz bandwidth, 2.048 MHz input, 8 kHz lock 40 www.semtech.com Revision 2.05/Jan 2001 a2001 Semtech Corp ACS8515 LC/P ADVANCED COMMUNCIATIONS Microprocessor interface timing SERIAL MODE In SERIAL mode, the device is configured to interface with a serial microprocessor bus. The following figures show the timing diagrams of write and read accesses for this mode. During read access the output data SDO is clocked out on the rising edge of SCLK when the active edge selection control bit CLKE is 0 and on the falling edge when CLKE = 1. Address, read/write control bit and write data are always clocked into the interface on the rising edge of SCLK. Both input data SDI and clock SCLK are oversampled, filtered and synchronized to the 6MHz internal clock. The serial interface clock (SCLK) is not required to run between accesses (i.e., when CSB = 1). CLKE = 0; SDO data is clocked out on the rising edge of SCLK FINAL CSB t su2 t pw2 t h2 SCLK t su1 t h1 _ R/W t pw1 SDI A0 A1 A2 A3 A4 A5 A6 t d1 t d2 SDO D0 D1 D2 D3 D4 D5 D6 D7 CLKE = 1; SDO data is clocked out on the falling edge of SCLK CSB t h2 SCLK SDI _ R/W A0 A1 A2 A3 A4 A5 A6 t d1 D0 D1 D2 D3 D4 D5 D6 D7 t d2 SDO Read access timing in SERIAL Mode. Revision 2.05/Jan 2001 a2001 Semtech Corp 41 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS Sy m b ol tsu1 tsu2 td 1 td 2 tp w 1 tp w 2 th 1 th 2 tp P ar am e t e r Setup SDI valid to SCLKrising edge Setup CSBfalling edge to SCLKrising edge Delay SCLKrising edge (SCLKfalling edge for CLKE = 1)to SDO valid Delay CSBrising edge to SDO h igh -Z SCLK low time SCLK h igh time Hold SDI valid after SCLKrising edge Hold CSB low after SCLKrising edge, for CLKE = 0 Hold CSB low after SCLKfalling edge, for CLKE = 1 Time b etw een consecutive accesses (CSBrising edge to CSBfalling edge) MIN 0 ns 160 ns 180 ns 180 ns 170 ns 5 ns 160 ns T YP - FINAL MA X 17 ns 10 ns - Read access timing in SERIAL Mode. C SB t su2 t pw 2 t h2 SC LK t su1 _ R/W t h1 t pw1 S DI A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 SD O Sy m b ol tsu1 tsu2 tp w 1 tp w 2 th 1 th 2 tp P ar am e t e r Setup SDI valid to SCLKrising edge Setup CSBfalling edge to SCLKrising edge SCLK low time SCLK high time Hold SDI valid after SCLKrising edge Hold CSB low after SCLKrising edge Time betw een consecutive accesses (CSBrising edge to CSBfalling edge) MIN 0 ns 160 ns 180 ns 180 ns 170 ns 5 ns 160 ns T YP - MA X - Write access timing in SERIAL Mode. Revision 2.05/Jan 2001 a2001 Semtech Corp 42 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS Package information FINAL D 2 3 D1 1 AN2 AN3 1 R1 S E 2 E1 1 3 4 L1 A A AN1 B R2 B Section A-A AN4 L 123 5 b e 7 Section B-B A A2 c 7 c1 7 Seating plane A1 6 b b1 7 8 Notes 1 2 3 The top package body may be smaller than the bottom package body by as much as 0.15 mm. To be determined at seating plane. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. Details of pin 1 identifier are optional but will be located within the zone indicated. Exact shape of corners can vary. A1 is defined as the distance from the seating plane to the lowest point of the package body. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. Shows plating. 4 5 6 7 8 Revision 2.05/Jan 2001 a2001 Semtech Corp 43 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS FINAL D i m e n si o n s in mm 64 L Q F P P ac k ag e D/E D 1/ E 1 A A1 A2 e AN1 AN2 AN3 AN4 R1 R2 L L1 S b b1 c c1 Mi n N om Max 12.00 10.00 1.40 1.50 1.60 0.05 0.10 0.15 1.35 1.40 1.45 0.50 11 12 13 11 12 13 0 - 0 3.5 7 0.08 - 0.08 0.20 0.45 0.60 0.75 1.00 (ref) 0.20 - 0.17 0.22 0.27 0.17 0.20 0.23 0.09 0.20 0.09 0.16 Thermal conditions The device is rated for full temperature range when this package is used with a 4 layer or more PCB. Copper coverage must exceed 50%. All pins must be soldered to the PCB. Maximum operating temperature must be reduced when the device is used with a PCB with less than these requirements. NOTES Revision 2.05/Jan 2001 a2001 Semtech Corp 44 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS Application information A simplified Application Schematic for the ACS8515 is illustrated in Figure 9. FINAL UvphyArA yApr Q $ W99$ D8! " W99 W99" W996 9,1 9287 *1' ! W99! @a '% rfprp 8! a9 a9 A 8" A 8# AfU6IU 8% A 8& A 9BI9! 9BI9 9BI9" 6BI9 PvhyAQprA vrshprAprpv TS8TX DIUS@R P! 9BI9 W99 A 8( 9BI9 W99 6BI9 S Y ! qq %%%#fp tq! !'HC " tq 9BI9" S# 9BI9 S 8! A 6BI9 # W99" $ W996 8 A S 8 A ! " # $ % & ' ( ! " # $ % D8 6 , , , , , '9 2, 9 '6 , , , 2 & & & & & *' & ' *' & & & 1 1 ' ' 1 2 6 ' ' 7 7 7 ' ''& , 2. + % 6BI9BS 6BI96 W6 DIUS@R S@A8GF 9BI99 W99 W99" 9BI99" 9BI99! W99! TS8TX W6! 6BI96! D8! 68T'$ $ D8 # QPS7 T8GF W99% W99$ 8T7 T9D 8GF@ D8UHT 9BI9" W99# W99" D8USTU W99! D8TI8" T@8" #' #& #% #$ ## #" #! # # "( "' "& "% "$ "# "" 8' A 9BI9 T9P T8GF 8T7 T9D 8GF@ W99 PvhyAQprA vrshprAprpv 8" A 9BI9 D8TI8! ) ) 6 *6 * ) ) 2( 2( F , , 313 . F Q 6 *''B B B 19 Q \ 2( B B & ' 9BI9 6 \ U 3 1''&&&&'1&&1' 6 U ) 1'( ( ( ( '< ( ( *' ) 02 2 *9 6 6 6 6 9 6 6 6 ' 9 vhyAA yArrqrqAsA $Arpv W99! W99$ 8$ A W99 8# 9BI9! A 9BI9 ATp HATp PQ PI T@8 Q T@8 I T@8!Q T@8!I TI8!x T@8 T@8! T@8" 9BI9! 9BI9 Figure 9: A simplified Application Schematic. Revision 2.05/Jan 2001 a2001 Semtech Corp 45 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS Revision History Changes from revision 2.04 to 2.05, January 2001. I t em 1 2 3 4 5 6 7 S e ct i o n Tab le of contents Register descrip tion Register descrip tion Register descrip tion Register descrip tion Holdover mode Revision History P ag e 2 20 22 24 25 31 46 Inclusion of Revision History sts_interrup ts register re-formatted cnfg_op erating_mode register error corrected cnfg_differential_outp uts error corrected cnfg_freq_limit register re-formatted and re-w ritten Sp elling error corrected Section added D e scr i p t i o n FINAL Revision 2.05/Jan 2001 a2001 Semtech Corp 46 www.semtech.com ACS8515 LC/P ADVANCED COMMUNCIATIONS Ordering information FINAL PA R T N U M B E R A CS8515 DE SCR I P T I O N SON ET/SDH Line Card Protection, 64 p in LQFP Disclaimers Life support - This product is not designed or intended for use in life suport equipment, devices or systems, or other critical applications. This product is not authorized or warranted by Semtech Corporation for such use. Right to change - Semtech Corporation reserves the right to make changes, without notice, to this product. Customers are advised to obtain the latest version of the relevant information before placing orders. For additional information, contact the following: Semtech Corporation Advanced Communications Products E-Mail: Internet: USA: AdvCom@semtech.com http://www.semtech.com 652 Mitchell Road, Newbury Park, CA 91320-2289 Tel: +1 805 498 2111, Fax: +1 805 498 3804 FAR EAST: 11F, No. 46, Lane 11, Kuang Fu North Road, Taipei, Taiwan, R.O.C. Tel: +886 2 2748 3380, Fax: +886 2 2748 3390 EUROPE: Delta House, Chilworth Science Park, Southampton, Hants, SO16 7NS, UK Tel: +44 23 80 769008, Fax: +44 23 80 768612 ISO9001 CERTIFIED Revision 2.05/Jan 2001 a2001 Semtech Corp 47 www.semtech.com |
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